MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 304

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 390. D2DI Control Register 1 (D2DCTL1)
Functional Description and Application Information
Table 389. D2DCTL0 Register Field Descriptions (continued)
The Clock Divider will provide the waveforms as shown in
is shorter than 50% or equal but never longer, since this is beneficial for the transaction speed.
4.37.3.2.2
This register is used to enable the D2DI interrupt and set number of D2DCLK cycles before a timeout error is asserted.
Table 391. D2DCTL1 Register Field Descriptions
Freescale Semiconductor
D2DCLKDIV
Reset
bus clock
0x00D9
a
D2DIE
D2DSWAI
Field
W
R
6:4
Field
7
4:2
1:0
5
00
01
10
11
D2D Interrupt Enable — Enables the external interrupt
0 External Interrupt is disabled
1 External Interrupt is enabled
Reserved, should be written to 0 to ensure compatibility with future versions of this interface.
D2DIE
D2D Stop In Wait — Controls the WAIT behavior. This bit can be written at any time.
0 Interface clock continues to run if the CPU enters WAIT mode
1 Interface clock stops if the CPU enters WAIT mode.
Reserved, should be written to 0 to ensure compatibility with future versions of this interface.
Interface Clock Divider — Determines the frequency of the interface clock. These bits are write-once in normal modes and
00
01
10
11
7
0
D2DI Control Register 1 (D2DCTL1)
“Write once“ means that after writing D2DCNTL0.D2DEN = 1 the write accesses to these
bits have no effect.
can be always written in special modes. See
Encoding 0. Bus clock divide by 1.
Encoding 1. Bus clock divide by 2.
Encoding 2. Bus clock divide by 3.
Encoding 3. Bus clock divide by 4.
Figure 95. Interface Clock Waveforms for Various D2DCLKDIV Encoding
6
0
0
0
0
5
Figure
NOTE
Figure 95
0
0
4
Description
95. The duty cycle of the clock is not always 50%, the high cycle
Description
for details on the clock waveforms
0
3
0
2
TIMOUT[3:0]
Die-to-Die Initiator (D2DIV1)
1
0
Access: User read/write
MM912F634
0
0
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