MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 241

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Functional Description and Application Information
4.31.4.6
A tag follows program information as it advances through the instruction queue. When a tagged instruction reaches the head of
the queue, a tag hit occurs and can initiate a state sequencer transition.
Each comparator control register features a TAG bit, which controls whether the comparator match causes a state sequencer
transition immediately or tags the opcode at the matched address. If a comparator is enabled for tagged comparisons, the
address stored in the comparator match address registers must be an opcode address.
Using Begin trigger together with tagging, if the tagged instruction is about to be executed, then the transition to the next state
sequencer state occurs. If the transition is to the Final State, tracing is started. Only upon completion of the tracing session can
a breakpoint be generated. Using End alignment, when the tagged instruction is about to be executed and the next transition is
to Final State, then a breakpoint is generated immediately before the tagged instruction is carried out.
R/W monitoring is not useful for tagged operations, since the taghit occurs based on the tagged opcode reaching the execution
stage of the instruction queue. Similarly access size (SZ) monitoring and data bus monitoring is not useful if tagging is selected,
since the tag is attached to the opcode at the matched address, and is not dependent on the data bus nor on the size of access.
Thus these bits are ignored if tagging is selected.
When configured for range comparisons and tagging, the ranges are accurate only to word boundaries.
Tagging is disabled when the BDM becomes active.
4.31.4.7
It is possible to generate breakpoints from channel transitions to Final State or using software to write to the TRIG bit in the
DBGC1 register.
4.31.4.7.1
Breakpoints can be generated when the state sequencer transitions to the Final State. If configured for tagging, then the
breakpoint is generated when the tagged opcode reaches the execution stage of the instruction queue.
If a tracing session is selected by the TSOURCE bit, breakpoints are requested when the tracing session has completed, thus if
Begin aligned triggering is selected, the breakpoint is requested only on completion of the subsequent trace (see
no tracing session is selected, breakpoints are requested immediately.
If the BRK bit is set, then the associated breakpoint is generated immediately independent of tracing trigger alignment.
Table 317. Breakpoint Setup For CPU Breakpoints
Freescale Semiconductor
BRK
0
0
0
0
1
1
Breakpoints
Tagging
Breakpoints From Comparator Channels
TALIGN
0
0
1
1
x
x
DBGBRK
0
1
0
1
1
0
Terminate tracing and generate breakpoint immediately on trigger
Fill Trace Buffer until trigger, then breakpoint request occurs
Fill Trace Buffer until trigger, then disarm (no breakpoints)
A breakpoint request occurs when Trace Buffer is full
Start Trace Buffer at trigger (no breakpoints)
Terminate tracing immediately on trigger
Start Trace Buffer at trigger
Breakpoint Alignment
S12S Debug (S12SDBGV1) Module
Table
MM912F634
317). If
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