MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 77

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Note:
Functional Description and Application Information
4.8.2.3
Table 89. Wake-up Source Register (WSR)
Reading the WSR will clear the wake-up status bit(s). Writing will have no effect. The Wake-up Source Register (WSR) has to be
read after a wake-up condition, in order to execute a new STOP mode command. Two base clock cycles (f
required between the WSR read and the MCR write.
Freescale Semiconductor
Offset
75.
Table 90. WSR - Register Field Descriptions
W
R
6 - LINWU
5 - L5WU
4 - L4WU
3 - L3WU
2 - L2WU
1 - L1WU
0 - L0WU
7 - FWU
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
(75)
Field
0x14
FWU
7
Wake-up Source Register (WSR)
Forced Wake-up - Wake-up caused by a forced wake-up
LIN Wake-up - Wake-up caused by a LIN wake-up
L5 Wake-up - Wake-up caused by a state change of the L6 Input
L4 Wake-up - Wake-up caused by a state change of the L5 Input
L3 Wake-up - Wake-up caused by a state change of the L4 Input
L2 Wake-up - Wake-up caused by a state change of the L3 Input
L1 Wake-up - Wake-up caused by a state change of the L2 Input
L0 Wake-up - Wake-up caused by a state change of the L1 Input
LINWU
6
L5WU
5
L4WU
4
Description
L3WU
3
L2WU
2
Wake-up / Cyclic Sense
L1WU
1
BASE
Access: User read
) delays are
MM912F634
L0WU
0
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