MM912H634DM1AER2 Freescale Semiconductor, MM912H634DM1AER2 Datasheet - Page 112

• Manufacturer Part Number: MM912H634DM1AER2
• Description: 16-bit Microcontrollers - MCU 64KS12 LIN2XLS/HS ISENSE
• Manufacturer: Freescale Semiconductor

Specifications of MM912H634DM1AER2

• Rohs: yes
• Core: HCS12
• Processor Series: MM912F634
• Data Bus Width: 16 bit
• Maximum Clock Frequency: 20 MHz
• Program Memory Size: 32 KB
• Data Ram Size: 2 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 5.5 V to 18 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-48
• Mounting Style: SMD/SMT
• A/d Bit Size: 10 bit
• A/d Channels Available: 15
• Interface Type: SPI
• Maximum Operating Temperature: + 105 C
• Minimum Operating Temperature: - 40 C
• Number Of Programmable I/os: 15
• Number Of Timers: 1
• Program Memory Type: Flash
• Supply Voltage - Max: 18 V
• Supply Voltage - Min: 5.5 V

Table 124. SCI Baud Rate Register (SCIBD (hi))
Table 126. SCI Baud Rate Register (SCIBDL)
Note:
Note:
Functional Description and Application Information
4.15.2
The SCI has eight 8-bit registers to control baud rate, select SCI options, report SCI status, and for transmit/receive data.
Refer to
This section refers to registers and control bits only by their names.
4.15.2.1
This pair of registers controls the prescale divisor for SCI baud rate generation. To update the 13-bit baud rate setting
[SBR12:SBR0], first write to SCIBD (hi) to buffer the high half of the new value, and then write to SCIBD (lo). The working value
in SCIBD (hi) does not change until SCIBD (lo) is written.
SCIBDL is reset to a non-zero value, so after reset the baud rate generator remains disabled until the first time the receiver or
transmitter is enabled (RE or TE bits in SCIC2 are written to 1).
Table 125. SCIBD (hi) Field Descriptions
Table 127. SCIBDL Field Descriptions
Freescale Semiconductor
Offset
Offset
96.
97.
Reset
Reset
RXEDGIE
SBR[128]
SBR[7:0]
W
W
LBKDIE
R
R
Field
Field
4:0
7:0
(96)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
(97)
Offset related to 0x0200 for blocking access and 0x300 for non blocking access within the global address space.
7
6
Section 4.5, “Die to Die Interface - Target"
0x40
0x41
LBKDIE
SBR7
Register Definition
LIN Break Detect Interrupt Enable (for LBKDIF)
0 Hardware interrupts from LBKDIF disabled (use polling).
1 Hardware interrupt requested when LBKDIF flag is 1.
RxD Input Active Edge Interrupt Enable (for RXEDGIF)
0 Hardware interrupts from RXEDGIF disabled (use polling).
1 Hardware interrupt requested when RXEDGIF flag is 1.
Baud Rate Modulo Divisor — The 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide rate
for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When BR = 1
to 8191, the SCI baud rate = BUSCLK/(16BR). See also BR bits in
Baud Rate Modulo Divisor — These 13 bits in SBR[12:0] are referred to collectively as BR, and they set the modulo divide
rate for the SCI baud rate generator. When BR = 0, the SCI baud rate generator is disabled to reduce supply current. When
BR = 1 to 8191, the SCI baud rate = BUSCLK/(16BR). See also BR bits in
SCI Baud Rate Registers (SCIBD (hi), SCIBD (lo))
7
0
7
0
RXEDGIE
SBR6
6
0
6
0
SBR5
0
0
0
5
5
of this data sheet for the absolute address assignments for all SCI registers.
SBR12
SBR4
0
0
4
4
Description
Description
SBR11
SBR3
0
0
3
3
Table
Serial Communication Interface (S08SCIV4)
127.
Table
SBR10
125.
SBR2
0
1
2
2
SBR9
SBR1
1
0
1
0
Access: User read/write
Access: User read/write
MM912F634
SBR8
SBR0
0
0
0
0
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