MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1023

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

17.4.1.3
The PCI bus arbiter has a feature that allows it to lock out any masters that are broken or ill-behaved. The
broken master feature is controlled by programming bit 12 of the PCI bus arbitration control register (0 =
enabled, 1 = disabled).
When the broken master feature is enabled, a granted device that does not assert PCI_FRAME within 16
PCI clock cycles after the bus is idle, has its grant removed and subsequent requests are ignored until its
REQ is negated for at least one clock cycle. This prevents ill-behaved masters from monopolizing the bus.
When the broken master feature is disabled, a device that requests the bus and receives a grant never loses
its grant until and unless it begins a transaction or negates its REQ signal. Note that disabling the broken
master feature is not recommended.
17.4.1.4
In the sleep power-saving mode, the clock signal driving SYSCLK can be disabled. If the clock is disabled,
the arbitration logic is not able to perform its function. System programmers must park the bus with a
device that can sustain the PCI_AD[31:0], PCI_C/BE[3:0], and parity signals prior to disabling the
SYSCLK signal. If the bus is parked on the MPC8533E when its clocks are stopped, the MPC8533E
sustains the PCI_AD[31:0], PCI_C/BE[3:0], and parity signals in their prior states. In this situation, the
only way for another agent to use the PCI bus is by waking the MPC8533E. In nap and doze power-saving
modes, the arbiter continues to operate allowing other PCI devices to run transactions.
17.4.2
This section provides a general description of the PCI bus protocol. Specific PCI bus transactions are
described in
and
All signals are sampled on the rising edge of the PCI bus clock (SYSCLK). Each signal has a setup and
hold aperture with respect to the rising clock edge in which transitions are not allowed. Outside this
aperture, signal values or transitions have no significance. See the separate hardware specifications
document for specific setup and hold times.
17.4.2.1
The basic PCI bus transfer mechanism is a burst. A burst is composed of an address phase followed by one
or more data phases. Fundamentally, all PCI data transfers are controlled by three signals—PCI_FRAME
(frame), PCI_IRDY (initiator ready), and PCI_TRDY (target ready). An initiator asserts PCI_FRAME to
indicate the beginning of a PCI bus transaction and negates PCI_FRAME to indicate the end of a PCI bus
transaction. An initiator negates PCI_IRDY to force wait cycles. A target negates PCI_TRDY to force wait
cycles.
The PCI bus is considered idle when both PCI_FRAME and PCI_IRDY are negated. The first clock cycle
in which PCI_FRAME is asserted indicates the beginning of the address phase. The address and bus
command code are transferred in that first cycle. The next cycle begins the first of one or more data phases.
Data is transferred between initiator and target in each cycle that both PCI_IRDY and PCI_TRDY are
Freescale Semiconductor
Figure 17-52
PCI Bus Protocol
Section 17.4.2.7, “PCI Bus Transactions.”
Broken Master Lock-Out
Power-Saving Modes and the PCI Arbiter
Basic Transfer Control
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
for examples of the transfer-control mechanisms described in this section.
Refer to
Figure
17-49,
Figure
17-50,
Figure
PCI Bus Interface
17-51,
17-45