MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1086

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PCI Express Interface Controller
18.3.6.6
Together with the other PCI Express error capture registers, PEX_ERR_CAP_R1 allows vital error
information to be captured when an error occurs. Different error information is reported depending on
whether the error source is from an outbound transaction from an internal source or from an inbound
transaction from an external source; the source of the captured error is reflected in
PEX_ERR_CAP_STAT[GSID]. Note that after the initial error is captured, no further capturing is
performed until the PEX_ERR_CAP_STAT[ECV] bit is clear.
PEX_ERR_CAP_R1 for the case when the error is caused by an outbound transaction from an internal
source (that is, PEX_ERR_CAP_STAT[GSID] ≠ 0h02), is shown in
Table 18-29
outbound transaction from an internal source.
PEX_ERR_CAP_R1 for the case when the error is caused by an inbound transaction from an external
source (that is, PEX_ERR_CAP_STAT[GSID] = 0h02 for controller 1), is shown in
18-38
24–31
0–23
Bits
Offset 0xE2C
Offset 0xE2C
Reset
Reset
Name
OD0
W
W
R
—
R
describes the fields of PEX_ERR_CAP_R1 for the case when the error is caused by an
PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
0
Figure 18-30. PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)
Figure 18-31. PCI Express Error Capture Register 1 (PEX_ERR_CAP_R1)
Reserved
Internal platform header bits 71-64. Contains internal platform header bit 71:64. Note that this field is only
valid for outbound internal platform errors. It is not valid for completion time-out errors or
PEX_CONFIG_ADDR/PEX_CONFIG_DATA errors.
30–31
26–29
25
24
Table 18-29. PCI Express Error Capture Register 1 Field Descriptions
Cls
Tag for read and non-posted write. Reserved otherwise.
Reserved
With Response (1 for read and non-posted write)
Internal Source, Outbound Transaction
Internal Source, Outbound Transaction
External Source, Inbound Transaction
—
All zeros
All zeros
GH1
Description
Figure
18-30.
23 24
Access: Read/Write
Access: Read/Write
Freescale Semiconductor
Figure
OD0
18-31.
31
31