MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1214

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Device Performance Monitor
20-20
ECM dispatch to CCSR
ECM dispatch write
ECM dispatch write allocate
ECM dispatch read
ECM dispatch read atomic clr, set, dec,
inc
ECM data bus grant DDR
ECM data bus grant PCI/PEX/DMA
ECM data bus grant I
ECM data bus grant LBC
ECM data bus grant eTSEC1
ECM data bus grant eTSEC3
ECM global data bus beat
ECM e500 direct read bus beat
ECM e500 direct read bus beat
forwarded
ECM cancel
Security/boot sequencer requests
Security/boot sequencer read requests
Security/boot sequencer data beats
Security/boot sequencer read data
beats
Security/boot sequencer request less
than 32 bytes
PIC total interrupt count
PIC interrupt wait cycles
PIC interrupt service cycles
PIC interrupt select 0 (duration
threshold)
PIC interrupt select 1 (duration
threshold)
PIC interrupt select 2 (duration
threshold)
PIC interrupt select 3 (duration
threshold)
Event Counted
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
C/Security
Table 20-10. Performance Monitor Events (continued)
Interrupt Controller (PIC) Events
Number
C1:119
C8:126
C1:120
C3:123
C5:119
C6:124
Ref:16
Ref:17
Ref:18
Ref:26
C2:84
C1:81
C2:85
C4:87
C9:87
C1:82
C2:86
C3:86
C1:83
C2:87
C4:89
C2:88
C2:76
C3:75
C4:79
C7:76
C2:83
—
—
—
—
—
—
—
—
—
—
—
—
—
ECM direct read bus beat forwarded directly to e500 R1 data
bus
—
Number of sequencer requests (total)
Number of sequencer read requests
Number of sequencer data beats (total)
Number of sequencer read data beats
Number of sequencer requests less than 32 bytes
Total number of interrupts serviced
Counts cycles when an interrupt waits to be acknowledge
Number of cycles there is an interrupt currently being serviced.
THRESHOLD: select 0–3: interrupt count over threshold. (Note:
only unmasked, nonzero priority requests are acknowledged).
The four interrupts are selected through register pairs,
PM0MR n –PM3MR n . See
Monitor Mask Registers (PMMRs).”
Description of Event Counted
Section 10.3.4, “Performance
Freescale Semiconductor