MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 256

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Core Register Summary
6-40
34–35
42–43
44–45
46–47
Bits
32
33
36
37
38
39
40
41
Name
TRAP Trap debug event enable
DAC1 Data address compare 1 debug event enable
DAC2 Data address compare 2 debug event enable
ICMP
IRPT
IAC1
IAC2
RST
BRT
IDM
—
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved, should be cleared.
Internal debug mode
0 Debug interrupts are disabled. No debug interrupts are taken and debug events are not logged.
1 If MSR[DE] = 1, the occurrence of a debug event or the recording of an earlier debug event in the DBSR
Programming note: Software must clear debug event status in the DBSR in the debug interrupt handler
when a debug interrupt is taken before re-enabling interrupts through MSR[DE]. Otherwise, redundant debug
interrupts are taken for the same debug event.
Reset. The e500 implements these bits as follows:
0 x Default (No action)
1 x Causes a hard reset if MSR[DE] and DBCR0[IDM] are set. Always cleared on subsequent cycle. This
Instruction completion debug event enable
0 ICMP debug events are disabled
1 ICMP debug events are enabled
Note: Instruction completion does not cause an ICMP debug event if MSR[DE] = 0.
Branch taken debug event enable
0 BRT debug events are disabled
1 BRT debug events are enabled
Note: Taken branches do not cause a BRT debug event if MSR[DE] = 0.
Interrupt taken debug event enable. This bit affects only noncritical interrupts.
0 IRPT debug events are disabled
1 IRPT debug events are enabled
0 TRAP debug events cannot occur
1 TRAP debug events can occur
Instruction address compare 1 debug event enable
0 IAC1 debug events cannot occur
1 IAC1 debug events can occur
Instruction address compare 2 debug event enable
0 IAC2 debug events cannot occur
1 IAC2 debug events can occur
Reserved, should be cleared.
00 DAC1 debug events cannot occur
01 DAC1 debug events can occur only if a store-type data storage access
10 DAC1 debug events can occur only if a load-type data storage access
11 DAC1 debug events can occur on any data storage access
00 DAC2 debug events cannot occur
01 DAC2 debug events can occur only if a store-type data storage access
10 DAC2 debug events can occur only if a load-type data storage access
11 DAC2 debug events can occur on any data storage access
when MSR[DE] = 0 or DBCR0[IDM] = 0 causes a debug interrupt.
causes a hard reset to the core only.
Table 6-35. DBCR0 Field Descriptions
Description
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