MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 192

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Core Complex Overview
5-8
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•
•
— 4-cycle floating-point add and subtract
The load/store unit (LSU) is shown in
The LSU has the following features:
— Three-cycle load latency
— Fully pipelined
— Load miss queue allows up to four load misses before stalling (up to nine load misses in the
— Load hits can continue to be serviced when the load miss queue is full.
— The seven-entry L1 store queue allows full pipelining of stores.
— The three-entry data line fill buffer (five-entry on the e500v2) is used for loads and cacheable
— The data write buffer contains three entries: one dedicated for snoop pushes, one dedicated for
Cache coherency
— Supports four-state cache coherency: modified-exclusive, exclusive, shared, and invalid
— Bus support for hardware-enforced coherency (bus snooping)
Core complex bus (CCB)—internal bus
— High-speed, on-chip local bus with data tagging
— 32-bit address bus
— Address protocol with address pipelining and retry/copyback derived from bus used by
e500v2).
stores. Stores are allocated here so loads can access data from the store immediately.
castouts, and one that can be used for snoop pushes or cast outs.
(MESI). Note, however that shared state may not be accessible in some implementations.
previous generations of processors (referred to as the 60x bus)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
To GPR operand bus
To completion queue
To GPRs
e500v1 (3 entry)
e500v2 (5 entry)
Figure 5-4. Three-Stage Load/Store Unit
Figure
Data Line
Fill Buffer
L1 Store
Three-Stage Pipeline
Queues and Buffers
To core interface unit
Queue
Load/Store Unit
Reservation
(64-/32-Bit)
Station
5-4.
Data Write
Queue
Buffer
Load
Miss
e500v2 (9 entry)
e500v1 (4 entry)
To data cache
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