MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 133

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

2.2.3.8
It is important to distinguish between the mapping function performed by the local access windows and
the additional mapping functions that happen at the target interface. The local access windows define how
a transaction is routed through the MPC8533E internal interconnects from the transactions source to its
target. After the transaction has arrived at its target interface, that interface controller may perform
additional mapping. For instance, the DDR SDRAM controller has chip select registers that map a memory
request to a particular external device. Similarly, the local bus controller has base registers that perform a
similar function. The PCI and PCI Express interfaces have outbound address translation and mapping units
that map the local address into an external address space.
These other mapping functions are configured by programming the configuration, control, and status
registers of the individual interfaces. Note that there is no need to have a one-to-one correspondence
between local access windows and chip select regions or outbound ATMU windows. A single local access
window can be further decoded to any number of chip selects or to any number or outbound ATMU
windows at the target interface.
2.2.3.9
If a local access window maps an address to an interface other than the DDR SDRAM controller, then there
should not be a valid chip select configured for the same address in the DDR SDRAM controller. Because
DDR SDRAM chip selects boundaries are defined by a beginning and ending address, it is easy to define
them so that they do not overlap with local access windows that map to other interfaces.
2.2.4
Outbound address translation and mapping refers to the translation of addresses from the local 36-bit
address space to the external address space and attributes of a particular I/O interface. On the MPC8533E,
the following blocks have outbound address translation and mapping units (ATMUs):
The PCI controller has four outbound ATMU windows plus a default window. The PCI outbound ATMU
registers include extended translation address registers so that up to 64 bits of external address space can
be supported. See
PCI outbound ATMU windows.
The PCI Express interface has four outbound ATMU windows plus a default window. The PCI Express
outbound ATMU registers include an extended translation address register so that up to 64 bits of external
address space can be supported.See
detailed description of the PCI Express outbound ATMU windows.
2.2.5
Inbound address translation and mapping refers to the translation of an address from the external address
space of an I/O interface (such as PCI address space) to the local 36-bit address space understood by the
Freescale Semiconductor
•
•
PCI
PCI Express
Outbound Address Translation and Mapping Windows
Inbound Address Translation and Mapping Windows
Distinguishing Local Access Windows from Other Mapping Functions
Illegal Interaction Between Local Access Windows and DDR
SDRAM Chip Selects
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Section 17.3.1.2, “PCI ATMU Outbound Registers,”
Section 18.3.5.1, “PCI Express Outbound ATMU Registers”
for a detailed description of the
Memory Map
for a
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