MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 494

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
12.3
The host processor maintains a record of current secure sessions and the corresponding keys and contexts
of those sessions. Once the host has determined that a security operation is required, it creates a descriptor
containing all the information the SEC needs to perform the security operation. The host creates the
descriptor in main memory, then writes a pointer to the descriptor into the fetch FIFO of one of the SEC
channels. The channel uses this pointer to read the descriptor into its descriptor buffer. Once it obtains the
descriptor, the SEC uses its bus mastering capability to obtain inputs and write results, thus off-loading
data movement and encryption operations from the host processor.
For test purposes, it is also possible for the host to write keys, context, and text-data directly to execution
units, using SEC’s host-controlled access. This method avoids the use of descriptors.
12.3.1
SEC descriptors are conceptually similar to descriptors used by most devices with DMA capability. The
descriptors have a fixed length of 64 bytes, i.e. eight 64-bit words (referred to as dwords). A descriptor
consists of one header dword and seven pointer dwords, as shown in
12-16
0x3_E800–0x3_EFFF KEUFIFO
Pointer dword 0
Pointer dword 1
Pointer dword 2
Pointer dword 3
Pointer dword 4
Pointer dword 5
Pointer dword 6
Header dword
Address Offset
(AD 17–0)
0x3_E140
0x3_E400
0x3_E408
0x3_E410
0x3_E418
Descriptor Overview
Descriptor Structure
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
0
KEUC6—KEU context_6 register
KEUKD1—KEU key data register_1
(CK-high)
KEUKD2—KEU key data register_2
(CK-low)
KEUKD3—KEU key data register_3
(IK-high)
KEUKD4—KEU key data register_4
(IK-low)
Length0
Length1
Length2
Length3
Length4
Length5
Length6
Table 12-3. SEC Address Map (continued)
15 16 17
Register
J0
J1
J2
J3
J4
J5
J6
Header
Figure 12-3. Descriptor Format
Extent0
Extent1
Extent2
Extent3
Extent4
Extent5
Extent6
23 24
—
—
—
—
—
—
—
27 28
Access
R/W
R/W
R/W
R/W
R/W
R/W
31 32
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0000
0x0000_0000_0000_0000
Figure
Reset
12-3.
Pointer0
Pointer1
Pointer2
Pointer3
Pointer4
Pointer5
Pointer6
Reserved
Freescale Semiconductor
12.4.7.13/12-89
12.4.7.14/12-89
12.4.7.14/12-89
12.4.7.15/12-90
12.4.7.15/12-90
12.4.7.16/12-90
Reference
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