MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 309

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Part III
Memory, Security, and I/O Interfaces
Part III defines the memory, security and I/O interfaces of the MPC8533E and it describes how these
blocks interact with one another and with other blocks on the device. The following chapters are included:
Freescale Semiconductor
•
•
•
•
•
•
•
Chapter 8, “e500 Coherency Module,”
communication between the e500 core complex, the L2 cache and the other blocks that comprise
the coherent memory domain of the MPC8533E.
The ECM provides a mechanism for I/O-initiated transactions to snoop the core complex bus
(CCB) of the e500 core in order to maintain coherency across cacheable local memory. It also
provides a flexible, easily expandable switch-type structure for e500- and I/O-initiated transactions
to be routed (dispatched) to target modules on the MPC8533E.
Chapter 9, “DDR Memory Controller,”
MPC8533E. This fully programmable controller supports most DDR memories available today,
including both buffered and unbuffered devices. The built-in error checking and correction (ECC)
ensures very low bit error rates for reliable high-frequency operation. Dynamic power management
and auto-precharge modes simplify memory system design. Special features like ECC error
injection support rapid system debug.
Chapter 10, “Programmable Interrupt Controller,”
interrupt controller (PIC) of the MPC8533E. This controller is an OpenPIC-compliant interrupt
controller that provides interrupt management, and is responsible for receiving hardware-generated
interrupts from different sources (both internal and external), prioritizing them, and delivering
them to the CPU for servicing.
Chapter 11, “I
MPC8533E. This synchronous, serial, bidirectional, multi-master bus allows two-wire connection
of devices such as microcontrollers, EEPROMs, real-time clock devices, A/D converters, and
LCDs. The MPC8533E powers up in boot sequencer mode which allows the I
initialize configuration registers.
Chapter 12, “Security Engine (SEC) 2.1,”
Chapter 13, “DUART,”
(UARTs) which feature a PC16552D-compatible programming model. These independent UARTs
are provided specifically to support system debugging.
Chapter 14, “Local Bus Controller,”
component of the local bus controller (LBC) is its memory controller which provides a seamless
interface to many types of memory devices and peripherals. The memory controller is responsible
for controlling eight memory banks shared by a high performance SDRAM machine, a
general-purpose chip-select machine (GPCM), and up to three user-programmable machines
(UPMs). As such, it supports a minimal glue logic interface to synchronous DRAM (SDRAM),
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
C Interfaces,”
describes the (dual) universal asynchronous receiver/transmitters
describes the two inter-IC (IIC or I
describes the local bus controller of the MPC8533E. The main
defines the e500 coherency module and how it facilitates
describes the DDR SDRAM memory controller of the
describes the security controller of the MPC8533E.
describes the embedded programmable
2
C) bus controllers of the
2
C1 controller to
III-1