MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 468

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

I
Note that the I
11.4.3
The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices can hold
SCL low after completion of a 1-byte transfer (9 bits). In such cases, it halts the bus clock and forces the
master clock into wait states until the slave releases the SCL line.
11.4.4
The clock control block handles requests from the clock signal for transferring and controlling data for
multiple tasks.
A 9-cycle data transfer clock is requested for the following conditions:
11.4.4.1
Due to the wire AND logic on the SCL line, a high-to-low transition on the SCL line affects all devices
connected on the bus. The devices begin counting their low period when the master drives the SCL line
low. After a device has driven SCL low, it holds the SCL line low until the clock high state is reached.
However, the change of low-to-high in a device clock may not change the state of the SCL line if another
device is still within its low period. Therefore, the synchronized clock signal, SCL, is held low by the
device with the longest low period. Devices with shorter low periods enter a high wait state during this
time. When all devices concerned have counted off their low period, the synchronized SCL line is released
and pulled high. Then there is no difference between the devices’ clocks and the state of the SCL line, and
all the devices begin counting their high periods. The first device to complete its high period pulls the SCL
line low again.
11.4.4.2
The following sections describes the synchronizing of the input signals, and the filtering of the SCL and
SDA lines in detail.
11-16
2
C Interfaces
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A start condition is attempted when the requesting device is not the bus owner
Unexpected STOP condition detected
Master mode
— Transmit slave address after START condition
— Transmit slave address after restart condition
— Transmit data
— Receive data
Slave mode
— Transmit data
— Receive data
— Receive slave address after START or restart condition
Handshaking
Clock Control
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
Clock Synchronization
Input Synchronization and Digital Filter
C module does not automatically retry a failed transfer attempt.
Freescale Semiconductor