MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 350

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

DDR Memory Controller
Table 9-17
above.
9-28
10–11 CKE_CNTL Clock enable control. Allows software to globally clear or set all CKE signals issued to DRAM. Once
12–15
16–31 MD_VALUE Mode register value. This field, which specifies the value that will be presented on the memory address pins
Bits
MD_VALUE
CKE_CNTL
SET_REF
SET_PRE
MD_SEL
CS_SEL
MD_EN
Field
Name
—
shows how DDR_SDRAM_MD_CNTL fields should be set for each of the tasks described
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
software has forced the value driven on CKE, that value will continue to be forced until software clears the
CKE_CNTL bits. At that time, the DDR controller will continue to drive the CKE signals to the same value
forced by software until another event causes the CKE signals to change (i.e., self refresh entry/exit, power
down entry/exit).
00 CKE signals are not forced by software.
01 CKE signals are forced to a low value by software.
10 CKE signals are forced to a high value by software.
11 Reserved
Reserved
of the DDR controller during a mode register set command, is significant only when this register is used to
issue a mode register set command or a precharge or precharge all command.
For a mode register set command, this field contains the data to be written to the selected mode register.
For a precharge command, only bit five is significant:
0 Issue a precharge command; MD_SEL selects the logical bank to be precharged
1 Issue a precharge all command; all logical banks are precharged
Select mode register.
See
Value written to mode
register
Mode Register Set
Table 9-16. DDR_SDRAM_MD_CNTL Field Descriptions (continued)
Table 9-16
Table 9-17. Settings of DDR_SDRAM_MD_CNTL Fields
1
0
0
0
.
Chooses chip select (CS)
Refresh
—
—
0
1
0
0
Description
Only bit five is significant.
See
Selects logical bank
Table 9-16
Precharge
0
0
1
0
.
See
Clock Enable Signals
Table 9-16
Freescale Semiconductor
Control
—
—
—
—
—
—
.