MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1234

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Debug Features and Watchpoint Facility
21.3.1
The following sections describe the control registers for the watchpoint monitor facility.
21.3.1.1
The watchpoint monitor control registers (WMCR0, WMCR1) shown in
control the specification of watchpoint monitor events.
21-10
0xE_200C WMAR—Watchpoint monitor address register
0xE_201C WMSR—Watchpoint monitor status register
0xE_204C TBAR—Trace buffer address register
0xE_205C TBSR—Trace buffer status register
0xE_20A0 PCIDR—Programmed context ID register
0xE_20A4 CCIDR—Current context ID register
0xE_20B0 TOSR—Trigger output source register
0xE_2014
0xE_2018
0xE_2040
0xE_2044
0xE_2054
0xE_2058
0xE_2060
0xE_2064
0xE_2068
Offset 0x000
Reset
Memory
Offset
Local
W
R
EN AMD TMD ECEN NECEN SIDEN TIDEN
0
WMAMR—Watchpoint monitor address mask register
WMTMR—Watchpoint monitor transaction mask register
TBCR0—Trace buffer control register 0
TBCR1—Trace buffer control register 1
TBAMR—Trace buffer address mask register
TBTMR—Trace buffer transaction mask register
TBACR—Trace buffer access control register
TBADHR—Trace buffer access data high register
TBADR—Trace buffer access data register
Watchpoint Monitor Register Descriptions
1
Watchpoint Monitor Control Registers 0–1 (WMCR0, WMCR1)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
2
Table 21-6. Debug and Watchpoint Monitor Memory Map (continued)
Figure 21-2. Watchpoint Monitor Control Register 0 (WMCR0)
3
4
Register
5
Trace Buffer Registers
Context ID Registers
6
Other Registers
7
All zeros
—
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Figure 21-2
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
20 21
Reset
STRT
Freescale Semiconductor
23 24
and
Access: Read/Write
Figure 21-3
21.3.1.2/21-12
21.3.1.3/21-13
21.3.1.4/21-13
21.3.1.5/21-15
21.3.2.1/21-15
21.3.2.1/21-15
21.3.2.2/21-18
21.3.2.3/21-18
21.3.2.4/21-19
21.3.2.5/21-19
21.3.2.6/21-20
21.3.2.7/21-21
21.3.2.8/21-21
21.3.3.1/21-22
21.3.3.2/21-23
21.3.4.1/21-23
Section/Page
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