MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 886

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
Reception errors are described in
15-156
Overrun error
Busy error
Filed frame to invalid
queue error
Parser error
Non-octet error
(dribbling bits)
CRC error
Memory read error
Data parity error
Babbling transmit error
Error
Error
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
The Ethernet controller maintains an internal FIFO buffer for receiving data. If a receiver FIFO buffer
overrun occurs, the controller sets RxBD[OV], sets RxBD[L], closes the buffer, increments the
discarded frame counter (RDRP), and sets IEVENT[RXF], The receiver then enters hunt mode
(seeking start of a new frame).
A frame is received and discarded due to a lack of buffers. The controller sets IEVENT[BSY] and
increments the discarded frame counter (RDRP). In addition, the RSTAT[QHLT n ] bit is set. RDRP will
increment for each frame that is received while the receiver is halted due to a busy condition. The
halted queue resumes reception once the RSTAT[QHLT n ] bit is cleared.
A frame is received and discarded as a result of the filer directing it to an RxBD ring that is currently
not enabled. The controller sets IEVENT[FIQ] and increments the discarded frame counter (RDRP).
If the receive frame parser is enabled, a parse error can be flagged as a result of inconsistencies dis-
covered between fields of the embedded packet headers. For example, the L2 header may indicate
an IPv4 header, but the IP version number fails to match. In the event of a parse error, parsing is ter-
minated at the inconsistent header, and the RxFCB[PERR] field indicates at which layer of the proto-
col stack the error was discovered. Receiver function continues regardless of parse errors, but
IEVENT[PERR] is set. The receive queue filer may operate with reduced or default information in
some cases; therefore, filer rule sets should be constructed so as to be tolerant of misformed frames.
Note: Any values in the length/type field between 1500 and 1536 will be treated as a length, however,
only illegal packets exist with this length/type since these are not valid lengths and not valid types.
These are treated by the MAC logic as out of range.
Software must confirm the parser and filer results by checking the type/length field after the packet has
been written to memory to see if it falls in this range.
The Ethernet controller handles a nibble of dribbling bits if the receive frame terminates as non-octet
aligned and it checks the CRC of the frame on the last octet boundary. If there is a CRC error, the
frame non-octet aligned (RxBD[NO]) error is reported, IEVENT[RXF] is set, and the alignment error
counter increments. The eTSEC relies on the statistics collector block to increment the receive
alignment error counter (RALN). If there is no CRC error, no error is reported.
If a CRC error occurs, the controller sets RxBD[CR], closes the buffer, and sets IEVENT[RXF]. This
eTSEC relies on the statistics collector block to record the event. After receiving a frame with a CRC
error, the receiver then enters hunt mode.
A system bus error occurred during a DMA transaction. The controller sets IEVENT[EBERR], DMA
stops sending data to the FIFO which causes an underrun error, and therefore TxBD[UN] is set, but
IEVENT[XFUN] is not set. The TSTAT[THLT] is set. Transmits are continued once TSTAT[THLT] is
cleared.
Data in the transmit FIFO was potentially corrupted. The controller sets IEVENT[DPE], but otherwise
continues transmission until halted explicitly.
A frame is transmitted which exceeds the MAC’s Maximum Frame Length and
MACCFG2[Huge Frame] is a 0. The controller sets IEVENT[BABT] and continues without interruption.
Table 15-137. Transmission Errors (continued)
Table
Table 15-138. Reception Errors
15-138.
Description
Response
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