MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1080

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

PCI Express Interface Controller
18.3.6.2
The PCI Express error interrupt enable register, shown in
when the corresponding PCI Express error detect register bits are set.
Table 18-24
18-32
24–31
Bits
0–7
Bits
10
11
12
8
9
23
Offset 0xE08
Reset
Reset
W
W
R
R
CDNSCIE Completion with data not successful interrupt enable. When this bit is set and PEX_ERR_DR[CDNSC] = 1
PCACIE
CRSTIE MISIE IOISIE CISIE CIEPIE IOIEPIE OACIE IOIAIE
PNMIE
PCTIE
Name
Name
IOIA
—
—
16
—
0
describes the fields of the PCI Express error interrupt enable register.
PCI Express Error Interrupt Enable Register (PEX_ERR_EN)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 18-23. PCI Express Error Detect Register Field Descriptions (continued)
Table 18-24. PCI Express Error Interrupt Enable Register Field Descriptions
Figure 18-25. PCI Express Error Interrupt Enable Register (PEX_ERR_EN)
17
I/O invalid address. An outbound I/O transaction with a translated address of greater than 4 Gbytes was
detected.
1 A greater than 4-Gbyte I/O address was detected
0 No greater than 4-Gbyte I/O address detected
Reserved
Reserved
PCI Express completion time-out interrupt enable. When set and PEX_ERR_DR[PCT]=1 will generate an
interrupt.
1 Enable PCI Express completion time-out interrupt generation
0 Disable PCI Express completion time-out interrupt generation
Reserved
PCI Express CA completion interrupt enable. When set and PEX_ERR_DR[PCAC]=1 will generate an
interrupt.
1 Enable completion with CA status interrupt generation
0 Disable completion with CA status interrupt generation
PCI Express no map interrupt enable. When set and PEX_ERR_DR[PNM]=1 will generate an interrupt.
1 Enable no map PCI Express packet interrupt generation
0 Disable no map PCI Express packet interrupt generation
will generate an interrupt.
1 Enable completion with data non successful interrupt generation
0 Disable completion with data non successful interrupt generation
18
19
—
20
21
22
23
7
All zeros
All zeros
PCTIE
Description
24
Description
8
Figure
—
9
PCACIE
10
18-25, allows interrupts to be generated
PNMIE
11
CDNSCIE CRSNCIE ICCAIE IACAIE
—
12
Freescale Semiconductor
Access: Read/Write
13
14
15
31