MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 161
MPC8533EVTAQGA
Manufacturer Part Number
MPC8533EVTAQGA
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTAQGA
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.0GHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
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Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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4.2.2
Table 4-3
to blocks within the MPC8533E, and although some of their functionality is described in
“Clocking,” they are defined in detail in their respective chapters.
Note that there is also a CLK_OUT signal in the MPC8533E; the signal driven on the CLK_OUT pin is
selectable and described in
SYSCLK
Freescale Semiconductor
Signal I/O
RTC
I System clock/PCI clock (SYSCLK/PCI_CLK). SYSCLK is the primary clock input to the MPC8533E. It is the clock
I Real time clock. May be used (optionally) to clock the time base of the e500 core. The RTC timing specifications
describes the overall clock signals of the MPC8533E. Note that some clock signals are specific
source for the e500 core and for all devices and interfaces that operate synchronously with the core. It is multiplied
up with a phased-lock loop (PLL) to create the core complex bus (CCB) clock (also called the platform clock), which
is used by virtually all of the synchronous system logic, including the L2 cache, the DDR SDRAM and local bus
memory controllers, and other internal blocks such as the DMA and interrupt controllers. The CCB clock, in turn,
feeds the PLL in the e500 core and the PLL that creates the local bus memory clocks.
When the PCI interface is used, SYSCLK also functions as the PCI_CLK signal. Note that this is true whether the
MPC8533E is in agent or host mode. The MPC8533E does not provide a separate PCI_CLK output in host mode.
are given in the MPC8533E Integrated Processor Hardware Specifications , but the maximum frequency should be
less than one-quarter of the CCB frequency. See
(optionally) to clock the global timers in the programmable interrupt controller (PIC).
Clock Signals
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Timing Assertion/Negation—See the MPC8533E Integrated Processor Hardware Specifications for specific
Timing Assertion/Negation—See the MPC8533E Integrated Processor Hardware Specifications for specific
Table 4-3. Clock Signals—Detailed Signal Descriptions
timing information for this signal.
timing information for this signal.
Section 19.4.1.23, “Clock Out Control Register (CLKOCR).”
Section 4.4.4.4, “Real Time
Description
Clock.” This signal can also be used
Reset, Clocking, and Initialization
Section 4.4.4,
4-3
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