MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 282

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

L2 Look-Aside Cache/SRAM
Table 7-5
7.3.1.2.2
The L2 cache external write address registers extended address (L2CEWAREAn), shown in
contain the upper 4 bits of the 28-bit L2 cache external write base address.
Table 7-6
7.3.1.2.3
The L2CEWARn/L2CEWAREAn address registers work with the L2 cache external write control
registers 0–3 (L2CEWCRn), shown in
7-14
Offset 0x2_0014
Reset
Offset 0x2_0018
Reset
24–31
28–31
0–23
0–27
Bits
Bits
W
W
R
R
0x2_0024
0x2_0034
0x2_0044
0x2_0028
0x2_0038
0x2_0048
E LOCK
0
0
Figure 7-9. Cache External Write Address Registers Extended Address (L2CEWAREA n )
describes L2CEWARn fields.
describes the fields of L2CEWAREAn.
ADDR
ADDR
Name
Name
1
Figure 7-10. Cache External Write Control Registers (L2CEWCR0–L2CEWCR3)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
—
L2 Cache External Write Address Registers Extended Address 0–3
(L2CEWAREA n )
L2 Cache External Write Control Registers 0–3 (L2CEWCR n )
2
—
3
bits of the base address are in L2CEWAREA n [ADDR].
Reserved
Reserved
address is in L2CEWAR n [ADDR].
Contains the lower 24 bits of the 28-bit L2 cache external write base address. Note that the upper 4
Contains the upper 4 bits of the L2 cache external write base address. Note that the rest of the base
4
Table 7-6. L2CEWAREA n Field Descriptions
Table 7-5. L2CEWAR n Field Descriptions
Figure
7-10, to control cache external write functionality.
—
All zeros
All zeros
Description
Description
SIZMASK
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
27 28
Figure
ADDR
7-9,
31
31