MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 552

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
12.4.6.8
The AESU EU go register, shown in
After the final message block is written to the input FIFO, the EU go register must be written. The value
in the data size register is used to determine how many bits of the final message block (always 128) will
12-74
Bits Name
51
52
53
54
55
56
57
58
59
60
61
62
63
ERE
DSE
OFE
OFU Output FIFO underflow.
KSE
IFO
ME
IFE
AE
CE
—
—
IE
Internal error. An internal processing error was detected while the AESU was processing.
0 Internal error enabled
1 Internal error disabled
Early read error. The AESU IV register was read while the AESU was processing.
0 Early read error enabled
1 Early read error disabled
Context error. An AESU key register, the key size register, data size register, mode register, or IV register was
modified while the AESU was processing.
0 Context error enabled
1 Context error disabled
Key size error. An inappropriate value (non 16, 24 or 32 bytes) was written to the AESU key size register
0 Key size error enabled
1 Key size error disabled
Data size error. Indicates that the number of bits to process is out of range.
0 Data size error enabled
1 Data size error disabled
Mode error. Indicates that invalid data was written to a register or a reserved mode bit was set.
0 Mode error enabled
1 Mode error disabled
Address error. An illegal read or write address was detected within the AESU address space.
1 Address error disabled
0 Address error enabled
Output FIFO error. The AESU output FIFO was detected non-empty upon write of AESU data size register
0 Output FIFO non-empty error enabled
1 Output FIFO non-empty error disabled
Input FIFO error. The AESU input FIFO was detected non-empty upon generation of done interrupt
0 Input FIFO non-empty error enabled
1 Input FIFO non-empty error disabled
Reserved
Input FIFO overflow. The AESU input FIFO was pushed while full.
0 Input FIFO overflow error enabled
1 Input FIFO overflow error disabled
The AESU Output FIFO was read while empty.
0 Output FIFO underflow error enabled
1 Output FIFO underflow error disabled
Reserved
AESU EU Go Register (AESUEUG)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 12-43. AESU Interrupt Control Register Field Descriptions (continued)
Figure
12-54, is used to indicate an AES operation may be completed.
Description
Freescale Semiconductor