MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 859

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

A GMII interface has 28 signals (TSECn_GTX_CLK + _GTX_CLK125 included), as defined by the IEEE
802.3u standard, for connecting to an Ethernet PHY.
15.6.1.4
This section describes the reduced gigabit media-independent interface (RGMII) intended to be used
between the PHYs and the GMII MAC. The RGMII is an alternative to the IEEE802.3u MII, the
IEEE802.3z GMII and the TBI. The RGMII reduces the number of signals required to interconnect the
MAC and the PHY from a maximum of 28 signals (GMII) to 15 signals (GTX_CLK125 included) in a cost
effective and technology independent manner. To accomplish this objective, the data paths and all
associated control signals are multiplexed using both edges of the clock. For gigabit operation, the clocks
operate at 125MHz, and for 10/100 operation, the clocks operate at 2.5 MHz or 25 MHz, respectively. Note
that the GTX_CLK125 input must be provided at 125 MHz for an RGMII interface, regardless of operation
speed (1 Gbps, 100 Mbps, or 10 Mbps).
media-independent interface and the signals required to establish the gigabit Ethernet controllers’ module
connection with a PHY. The RGMII is implemented as defined by the RGMII specification Version 1.2a
9/22/00.
Freescale Semiconductor
1
The management signals (MDC and MDIO) are common to all of the Ethernet controllers’ connections
in the system, assuming that each PHY has a different management address.
eTSEC
Reduced Gigabit Media-Independent Interface (RGMII)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Gigabit Transmit Clock (TSEC n _GTX_CLK)
Gigabit Reference Clock (GTX_CLK125)
Transmit Nibble Data (TSEC n _TXD[7:0])
Receive Nibble Data (TSEC n _RXD[7:0])
Receive Data Valid (TSEC n _RX_DV)
Carrier Sense Output (TSEC n _CRS)
Figure 15-119. eTSEC-GMII Connection
Transmit Enable (TSEC n _TX_EN)
Transmit Clock (TSEC n _TX_CLK)
Receive Clock (TSEC n _RX_CLK)
Management Data Clock
Transmit Error (TSEC n _TX_ER)
Receive Error (TSEC n _RX_ER)
Management Data I/O
Figure 15-120
1
depicts the basic components of the gigabit reduced
1
(MDIO)
(MDC)
Enhanced Three-Speed Ethernet Controllers
Ethernet
Gigabit
PHY
Medium
15-129