MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 166

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Reset, Clocking, and Initialization
Table 4-8
4.3.2
The boot sequencer is a DMA engine that accesses a serial ROM on the I
CCSR memory or the memory space pointed to by the alternate configuration base address register
(ALTCBAR). See
enabled by reset configuration pins as described in
boot sequencer is enabled, the e500 core is held in reset until the boot sequencer has completed its
operation. For more details, see
4.4
This section describes the various ways to reset the MPC8533E, the POR configurations, and the clocking
on the device.
4.4.1
The MPC8533E has reset input signals for hard and soft reset operation.
4.4.1.1
Assertion of SRESET causes a machine check interrupt to the e500 core. When this occurs, the soft reset
flag is recorded in the machine check summary register (MCPSUMR) in the global utilities block so that
software can identify the machine check as a soft reset condition. See the e500 core family reference
manual for more information on the machine check interrupt and
Summary Register (MCPSUMR),”
SRESET is asserted before the e500 core is configured to handle a machine check interrupt, a core
checkstop condition occurs, which causes CKSTP_OUT to assert.
4.4.1.2
The MPC8533E can be completely reset by the assertion of the HRESET input. The assertion of this signal
by external logic is the equivalent of a POR and causes the sequence of events described in
“Power-On Reset Sequence.”
4-8
8–31
Bits
1–7
0
Functional Description
describes BPTR bit settings.
BOOT_PAGE
Boot Sequencer
Reset Operations
Name
Soft Reset
Hard Reset
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
EN
—
Section 4.3.1.2, “Accessing Alternate Configuration Space.”
Boot page translation enable
0 Boot page is not translated.
1 Boot page is translated as defined in the BPTR[BOOT_PAGE] parameter.
Write reserved, read = 0
Translation for boot page. If enabled, the high order 24 bits of accesses to 0x0_FFFF_F nnn are
replaced with this value.
Section 11.4.5, “Boot Sequencer Mode,”
for more information on the setting of the soft reset flag. Note that if
Table 4-8. BPTR Bit Settings
Section 4.4.3.8, “Boot Sequencer Configuration.”
Description
Section 19.4.1.14, “Machine Check
2
in the I
C interface and writes data to
The boot sequencer is
2
C chapter.
Freescale Semiconductor
Section 4.4.2,
If the