MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1218

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Device Performance Monitor
20-24
Number of cycles Rx FIFO > 1/4 full
Number of cycles Rx FIFO > 1/2 full
Number of cycles Rx FIFO > 3/4 full
Number of cycles Rx FIFO = full
Number of accepted frames match
Number of accepted frames to station
address
Number of accepted unicast frames via
has
Number of accepted group frames via
hash
Number of accepted farms via exact
match
Number of rejected frames at layer 2
Number of RX interrupts signalled
Number of TX interrupts signalled
RX data write lifetime (Duration
Threshold)
Number of RX packets received while
RX FIFO is full
Inbound G2PI read
Inbound G2PI write
Inbound G2PI data
Outbound G2PI read
Outbound G2PI write
Outbound G2PI data
Inbound Static Queue 0 start (Duration
Threshold)
Outbound Static Queue 0 start (Dura-
tion Threshold)
Inbound G2PI read
Event Counted
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 20-10. Performance Monitor Events (continued)
PCI Express 1 to OCeaN Gasket Events
PCI Express 2 to OCeaN Gasket Events
Number
C1:109
C2:116
C3:118
C8:102
C7:100
C4:111
C2:112
C8:119
C9:101
C5:124
C6:126
C7:125
C8:124
Ref:45
Ref:49
Ref:54
Ref:55
C9:97
C9:91
C6:90
C5:95
C3:85
C8:70
Number of cycles Rx FIFO > 1/4 full
Number of cycles Rx FIFO > 1/2 full
Number of cycles Rx FIFO > 3/4 full
Number of cycles Rx FIFO = full
—
—
—
—
—
—
—
—
—
—
A single pulse to indicate an inbound G2PI read has occurred.
A single pulse to indicate an inbound G2PI write has occurred.
A level signal to indicate the amount of data transferred if any
for inbound G2PI request. Active for every beat of G2PI data.
A single pulse to indicate an outbound G2PI read has
occurred.
A single pulse to indicate an outbound G2PI write has
occurred.
A level signal to indicate the amount of data transferred if any
for outbound G2PI request. Active for every beat of G2PI data.
Lifetime of ISQ entry 0 or 6.
Lifetime of OSQ entry 0.
A single pulse to indicate an inbound G2PI read has occurred.
Description of Event Counted
Freescale Semiconductor