MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1059

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MPC8533EVTAQGA

Manufacturer Part Number
MPC8533EVTAQGA
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTAQGA

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.0GHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8533EVTAQGA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
18.3.2.3
The PCI Express outbound completion timeout register, shown in
time for a response to come back as a result of an outbound non-posted request before a timeout condition
occurs.
The fields of the PCI Express outbound completion timeout register are described in
18.3.2.4
The PCI Express configuration retry timeout register, shown in
period during which retries of configuration transactions which resulted in a CRS response occur.
Freescale Semiconductor
Offset 0x00C
Reset 0
Offset 0x010
8–31
Reset 0
Bits
1–7
0
W
W
R
R
TD
RD
0
0
Name
Figure 18-4. PCI Express Outbound Completion Timeout Register (PEX_OTB_CPL_TOR)
TD
TC
Figure 18-5. PCI Express Configuration Retry Timeout Register (PEX_CONF_RTY_TOR)
0
1
0
1
0
PCI Express Outbound Completion Timeout Register
(PEX_OTB_CPL_TOR)
PCI Express Configuration Retry Timeout Register
(PEX_CONF_RTY_TOR)
0
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Timeout disable. This bit controls the enabling/disabling of the timeout function.
0 Enable completion timeout
1 Disable completion timeout
Reserved
Timeout counter. This is the value that is used to load the response counter of the completion timeout.
One TC unit is 24 ns at 333 MHz and 30 ns at 260 MHz.
Timeout period based on different TC settings:
0x00_0000
0x10_FFFF 26.72 ms at 333.33 MHz platform clock
0xFF_FFFF 446.94 ms at 333.33 MHz platform clock
0
0
3
0
0
4
0
1
0
0
Reserved
Table 18-6. PEX_OTB_CPL_TOR Field Descriptions
0
7
0
0
8
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
Description
1
1
1
1
TC
1
1
Figure
Figure
1
1
TC
1
1
18-5, contains the maximum time
18-4, contains the maximum wait
1
1
1
1
1
1
PCI Express Interface Controller
1
1
1
1
Table
1
1
Access: Read/Write
Access: Read/Write
1
1
18-6.
1
1
1
1
1
1
18-11
31
31
1
1

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