MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 700

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
For data timings, only the propagation delay of one buffer plus the actual data setup time has to be
considered.
14.5.2
Because the local bus uses multiplexed address and data, special consideration must be given to avoid bus
contention at bus turnaround. The following cases must be examined:
The bus does not change direction for the following cases so they need no special attention:
14.5.2.1
During a read cycle, the memory/peripheral drives the bus and the bus transceiver drives LAD. After the
data has been sampled, the output drivers of the external device must be disabled. This can take some time;
for slow devices the EHTR feature of the GPCM or the programmability of the UPM should be used to
guarantee that those devices have stopped driving the bus when the LBC memory controller ends the bus
cycle.
In this case, after the previous cycle ends, LBCTL goes high and changes the direction of the bus
transceiver. The LBC then inserts a bus turnaround cycle to avoid contention. The external device has now
already placed its data signals in high impedance and no bus contention will occur.
14.5.2.2
During the address phase, LAD actively drives the address and LBCTL is high, driving the bus
transceivers in the same direction as during a write. After the end of the address phase, LBCTL goes low
and changes the direction of the bus transceiver. The LBC places the LAD signals in high impedance after
its t
14-82
•
•
•
•
•
•
•
dis
(LB). The LBCTL will have its new state after t
Address phase after previous read
Read data phase after address phase
Read-modify-write cycle for parity protected memory banks
UPM cycles with additional address phases
Continued burst after the first beat
Write data phase after address phase
Address phase after previous write
Figure 14-72
Bus Turnaround
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Local Bus Interface
Address Phase After Previous Read
Read Data Phase After Address Phase
LAD[0:31]
shows the GPCM data timings.
LBCTL
Figure 14-72. GPCM Data Timings
Muxed Address/Data
Buffered Data
Buffer
en
(LB) and, because this is an asynchronous input,
D
Device
Signal
Input
Peripherals
Memories
Slower
Freescale Semiconductor
and