MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1245

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Table 21-20
21.3.2.7
The trace buffer access data high register (TBADHR), shown in
bits of the data read from the trace buffer during a software-initiated read command (TBACR[RD]), or the
write data to be written into the trace buffer during a software-initiated write command (TBACR[WR]).
TBACR must be configured to perform a read before this register contains valid data. This register must
be initialized by software before configuring the TBACR to perform a write command.
Table 21-21
21.3.2.8
The trace buffer access data register (TBADR), shown in
the data read from the trace buffer during a software-initiated read command (TBACR[RD]) or the write
data to be written into the trace buffer during a software-initiated write command (TBACR[WR]). TBACR
must be configured to perform a read before this register contains valid data. This register must be
initialized by software before configuring the TBACR to perform a write command.
Freescale Semiconductor
0–31
24–31
Bits
2–23
Bits
Offset 0x064
Reset
0
1
W
R
TBADH Trace buffer access data high. The higher 32 bits of the data read from or to be written into the trace buffer,
Name
0
Name
INDX
WR
RD
—
describes the TBACR fields.
describes TBADHR.
Trace Buffer Access Data High Register (TBADHR)
Trace Buffer Access Data Register (TBADR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
depending on whether the array is accessed with a read or a write.
Read command. When set, a trace buffer read is performed using the value of TBACR[INDX]. This bit is
automatically cleared when the read is performed.
Write command. When set, a trace buffer write is performed using the value of TBACR[INDX]. This bit is
automatically cleared when the write is performed. A write occurs only if the trace buffer is not active: write
requests are ignored while the buffer is active.
Reserved
Buffer index to read from or write into (0–255). Used in conjunction with TBACR[RD] and TBACR[WR].
Figure 21-15. Trace Buffer Read High Register (TBADHR)
Table 21-21. TBADHR Field Descriptions
Table 21-20. TBACR Field Descriptions
All zeros
TBADH
Description
Description
Figure
Figure
21-16, contains the low-order 32 bits of
21-15, contains the high-order 32
Debug Features and Watchpoint Facility
Access: Read/Write
31
21-21