MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 529

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

The MDEU mode register has two configurations, determined by the value of the NEW bit (see
Figure 12-29
types (1000_1, 1001_). The old configuration (NEW = 0) is used by all other descriptor types and is
backward compatible with SEC 2.0.
The mode register is cleared when the MDEU is reset or re-initialized. Setting a reserved mode bit
generated a data error. If the mode register is modified during processing, a context error is generated.
Table 12-26
Freescale Semiconductor
Address MDEU 0x3_6000
The following bits are described for information only. They are not under direct user control.
The following bits are controlled through the MODE0 or MODE1 fields of the descriptor header.
0–53
Bits
54
55
56
57
58
59
Reset
W
R
NEW=0 Determines the configuration of the MDEU mode register. This table shows the configuration for NEW=0.
CONT
SMAC
Name
0
CICV
INIT
—
—
describes the MDEU mode register fields in the old configuration.
and
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
Reserved. Must be set to zero.
Continue. Most operations require this bit to be cleared. It is set only when the data to be hashed is spread
across multiple descriptors.
The value programmed in PD must be opposite to the value in this bit.
0 Perform autopadding and complete the message digest. Used when the entire hash is performed with one
1 This hash will be continued in a subsequent descriptor. Do not autopad and do not complete the message
Compare integrity check values.
0 Normal operation; no ICV comparison.
1 After the message digest (ICV) is computed, compare it to the data in the MDEU’s input FIFO. If the ICVs
Only applicable to descriptor types that provide for reading an ICV in value.
Specifies whether to perform an SSL-MAC operation.
0 Normal operation
1 Perform an SSL3.0 MAC operation. This requires a key and key length. If this is set then the HMAC bit
Initialization bit. Most operations will require this bit to be set. Cleared only for operations that load context from
a known intermediate hash value.
0 Do not initialize digest registers. In this case the registers must be loaded from a hash context pointer in the
1 Do an algorithm-specific initialization of the digest registers.
descriptor, or on the last of a sequence of descriptors.
digest.
do not match, send an error interrupt to the channel. The number of bytes to be compared is given by the
ICV size register.
should be 0.
descriptor. When the data to be hashed is spread across multiple descriptors, this bit must be 0 on all but
the first descriptor.
Figure
Figure 12-29. MDEU Mode Register in Old Configuration (NEW = 0)
Table 12-26. MDEU Mode Register in Old Configuration (NEW = 0)
12-30). The new configuration (NEW = 1) is used only by TLS/SSL descriptor
—
All zeros
53
Description
NEW — CONT CICV SMAC INIT HMAC PD ALG
54
55
56
57
58
Security Engine (SEC) 2.1
59
Access: Read/Write
60
61
62 63
12-51