MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 740

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
15-10
EC_GTX_CLK125
TSEC n _RX_CLK
TSEC n _RX_DV
EC_MDIO
EC_MDC
Signal
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 15-2. eTSEC Signals—Detailed Signal Descriptions (continued)
I/O
I/O Management data input/output, BIDI
O
I
I
I
oscillator, or is sometimes provided by the PHY. EC_GTX_CLK125 is a 125-MHz input into the
eTSEC and is used to generate all 125-MHz related signals and clocks in the following modes:
This input is not used in MII, or RMII or FIFO modes.
Management data clock.
This signal is a clock (typically 2.5 MHz) supplied by the MAC in the following modes:
(IEEE set minimum period of 400 ns or a frequency of 2.5 MHz, but the device may be configured
up to 12.5 MHz if supported by the PHY at that speed.) The frequency can be modified by writing
to MIIMCFG[28:31] of the eTSEC1 controller.
Receive clock. In GMII, MII, or RGMII mode, the receive clock TSEC n _RX_CLK is a continuous
clock (2.5, 25, or 125 MHz) that provides a timing reference for TSEC n _RX_DV, TSEC n _RXD,
and TSEC n _RX_ER.
In TBI mode, TSEC n _RX_CLK is the input for a 62.5 MHz PMA receive clock, 0 split phase with
PMA_RX_CLK1 and is supplied by the SerDes.
In RTBI mode it is a 125-MHz receive clock.
In RMII mode this clock is not used for the receive clock, as RMII uses a shared reference clock.
In FIFO mode the receive clock is a continuous clock whose maximum is defined by a ratio of
4.2:1 (platform:RxClk) in GMII mode and a ratio of 3.2:1 (platform:RxClk) in encoded mode.
Receive data valid. In GMII or MII mode, if TSEC n _RX_DV is asserted, the PHY is indicating that
valid data is present on the GMII and MII interfaces.
In RGMII mode, TSEC n _RX_DV becomes RX_CTL. The RX_DV and RX_ERR are received on
this signal on the rising and falling edges of TSEC n _RX_CLK.
In TBI mode, TSEC n _RX_DV represents receive code group (RCG) bit 8. Together, with RCG[9]
and RCG[7:0], they represents the 10-bit encoded symbol of GMII receive signals.
In RTBI mode, TSEC n _RX_DV represents receive code group (RCG) bit 4 and 9. On the positive
edge of the TSEC n _RX_CLK, RCG[4] and RCG[3:0] represent the first half of the 10-bit encoded
symbol. On the negative edge of the TSEC n _RX_CLK, RCG[9] and RCG[8:5] represent the
second half of the 10-bit encoded symbol.
In RMII mode the PHY asserts TSEC n _RX_DV (CRS_DV) when the receive medium is non-idle.
This signal asserts asynchronously with respect to the RMII reference clock, but negates
synchronously to indicate loss of carrier.In FIFO mode TSEC n _RX_DV is used to indicate valid
data (GMII-style protocols) or forms part of the receive control flags (encoded packet protocols).
Gigabit transmit 125-MHz source. This signal must be generated externally with a crystal or
Meaning
• GMII
• TBI
• RTBI
• RGMII
• MII
• RMII
• TBI
• RTBI
• GMII
• RGMII
Timing Asserted/Negated—This signal is required to be synchronous with the EC_MDC
State
Asserted/Negated—In MII, RMII, TBI, RTBI, GMII, or RGMII mode EC_MDIO is a
bidirectional signal to input PHY-supplied status during management read cycles
and output control during MII management write cycles. Addressed using
eTSEC1 memory-mapped registers.
signal.
Description
Freescale Semiconductor