MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 569

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

processing, the input data is hashed with the integrity key and the resulting MAC is placed in the KEU data
out register. The output size is the same as the input size.
A write to anywhere in the KEU FIFO address space causes the 64-bit-word to be pushed onto the KEU
input FIFO, and a read from anywhere in the KEU FIFO address space causes a 64-bit-word to be popped
off of the KEU output FIFO. Overflows and underflows caused by reading or writing the KEU FIFOs are
reflected in the KEU interrupt status register.
12.5
A channel in the SEC manages the execution of each cryptographic task, making use of one or more of the
SEC’s execution units (EUs). Control information and data pointers for a given task are stored in the form
of a descriptor (see
descriptor determines what EUs are used, how they are configured, where to fetch needed data, and where
to store the results. To invoke cryptographic tasks, the host constructs a descriptor, selects a channel, and
writes a pointer to the descriptor into the selected channel’s fetch FIFO. The fetch FIFO can store up to 24
pointers. Operations performed by channels include the following (not necessarily in this order):
The channel waits indefinitely for the controller to complete a requested activity before continuing to the
next step of descriptor processing.
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If the channel is idle and its fetch FIFO is non-empty, read the next descriptor pointer from the fetch
FIFO, and use this pointer to read the descriptor into the channel’s descriptor buffer.
Request from the controller the assignment of one or more EUs for the exclusive use of the channel.
Where necessary, configure the secondary EU to snoop input or output data intended for the
primary EU.
Upon notification of completion of the EU reset sequence, initialize mode registers in the assigned
EU.
Initialize EUs and write to EU registers such as key size and text-data size.
Transfer data parcels (up to 32 Kbytes) from system memory into assigned EU input registers and
FIFOs. This may involve using link tables to gather input data that has been split into multiple
segments which are stored in various locations of system memory. For the RAID-XOR descriptor
type, the channel rotates among three data sources, fetching 32 bytes from each source.
Transfer data parcels (up to 32 Kbytes) from assigned EU output registers and FIFOs to system
memory space. This may involve using link tables to scatter output data into multiple segments
which are stored in various locations of system memory.
Initialize the EU go register (where applicable) in the assigned EU upon completion of last EU
write indicated by the descriptor. The channel waits for a indication from the EU that processing
of input text-data is complete before proceeding with further activity after writing EU go.
Reset assigned EU(s).
Release assigned EU(s).
When a descriptor has been completely processed, provide feedback to the host, in the form of
interrupt and/or descriptor header write-back to system memory.
When descriptor processing is halted due to an error, provide feedback to the host via interrupt.
Crypto-Channels
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Section 12.3.1, “Descriptor
Structure”) in system memory or in the channel itself. A
Security Engine (SEC) 2.1
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