MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 333

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

9.4.1
This section describes the DDR memory controller registers. Shading indicates reserved fields that should
not be written.
9.4.1.1
The chip select bounds registers (CSn_BNDS) define the starting and ending address of the memory space
that corresponds to the individual chip selects. Note that the size specified in CSn_BNDS should equal the
size of physical DRAM. Also, note that EAn must be greater than or equal to SAn.
If chip select interleaving is enabled, all fields in the lower interleaved chip select will be used, and the
other chip selects’ bounds registers will be unused. For example, if chip selects 0 and 1 are interleaved, all
fields in CS0_BNDS will be used, and all fields in CS1_BNDS will be unused.
CSn_BNDS are shown in
Table 9-6
9.4.1.2
The chip select configuration (CSn_CONFIG) registers shown in
and set the number of row and column bits used for each chip select. These registers should be loaded with
the correct number of row and column bits for each SDRAM. Because CSn_CONFIG[ROW_BITS_CS_n,
COL_BITS_CS_n] establish address multiplexing, the user should take great care to set these values
correctly.
If chip select interleaving is enabled, then all fields in the lower interleaved chip select will be used, and
the other registers’ fields will be unused, with the exception of the ODT_RD_CFG and ODT_WR_CFG
fields. For example, if chip selects 0 and 1 are interleaved, all fields in CS0_CONFIG will be used, but
only the ODT_RD_CFG and ODT_WR_CFG fields in CS1_CONFIG will be used.
Freescale Semiconductor
Offset 0x000, 0x008, 0x010, 0x018
Reset
16–19
20–31
4–15
Bits
0–3
W
R
0
Name
EA n
SA n
describes the CSn_BNDS register fields.
—
—
—
Register Descriptions
Chip Select Memory Bounds (CS n _BNDS)
Chip Select Configuration (CS n _CONFIG)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
Starting address for chip select (bank) n. This value is compared against the 12 msbs of the 36-bit address.
Reserved
Ending address for chip select (bank) n. This value is compared against the 12 msbs of the 36-bit address.
3
4
Figure 9-2. Chip Select Bounds Registers (CS n _BNDS)
Figure
Table 9-6. CS n_ BNDS Field Descriptions
9-2.
SA n
All zeros
15 16
Description
—
Figure 9-3
19 20
enable the DDR chip selects
EA n
DDR Memory Controller
Access: Read/Write
9-11
31