MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 31
MPC8533EVTAQGA
Manufacturer Part Number
MPC8533EVTAQGA
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTAQGA
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.0GHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8533EVTAQGA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
- MPC8533VTALF PDF datasheet
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Paragraph
Number
15.6.3.2
15.6.3.3
15.6.3.4
15.6.3.5
15.6.3.5.1
15.6.3.5.2
15.6.3.6
15.6.3.7
15.6.3.7.1
15.6.3.7.2
15.6.3.8
15.6.3.9
15.6.3.10
15.6.3.10.1
15.6.3.10.2
15.6.3.10.3
15.6.3.11
15.6.3.12
15.6.3.13
15.6.4
15.6.4.1
15.6.4.2
15.6.4.3
15.6.5
15.6.5.1
15.6.5.1.1
15.6.5.1.2
15.6.5.1.3
15.6.5.1.4
15.6.5.1.5
15.6.5.1.6
15.6.5.1.7
15.6.5.1.8
15.6.5.2
15.6.5.2.1
15.6.5.2.2
15.6.6
15.6.6.1
15.6.6.2
15.6.6.2.1
15.6.6.2.2
Freescale Semiconductor
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
TCP/IP Off-Load ................................................................................................... 15-157
Quality of Service (QoS) Provision ....................................................................... 15-162
Lossless Flow Control ........................................................................................... 15-170
Soft Reset and Reconfiguring Procedure........................................................... 15-142
Gigabit Ethernet Frame Transmission ............................................................... 15-143
Gigabit Ethernet Frame Reception .................................................................... 15-144
Ethernet Preamble Customization ..................................................................... 15-145
RMON Support.................................................................................................. 15-147
Frame Recognition............................................................................................. 15-147
Magic Packet Mode ........................................................................................... 15-151
Flow Control...................................................................................................... 15-151
Interrupt Handling ............................................................................................. 15-152
Inter-Frame Gap Time ....................................................................................... 15-155
Internal and External Loop Back ....................................................................... 15-155
Error-Handling Procedure.................................................................................. 15-155
Frame Control Blocks........................................................................................ 15-158
Transmit Path Off-Load..................................................................................... 15-158
Receive Path Off-Load ...................................................................................... 15-160
Receive Queue Filer .......................................................................................... 15-162
Transmission Scheduling................................................................................... 15-168
Back Pressure Determination via Free Buffers.................................................. 15-170
Software Use of Hardware-Initiated Back Pressure .......................................... 15-172
User-Defined Preamble Transmission ........................................................... 15-146
User-Visible Preamble Reception.................................................................. 15-146
Destination Address Recognition and Frame Filtering ................................. 15-147
Hash Table Algorithm.................................................................................... 15-149
Interrupt Coalescing ...................................................................................... 15-153
Interrupt Coalescing By Frame Count Threshold.......................................... 15-153
Interrupt Coalescing By Timer Threshold ..................................................... 15-154
Filing Rules ................................................................................................... 15-163
Comparing Properties with Bit Masks........................................................... 15-164
Special-Case Rules ........................................................................................ 15-165
Filer Interrupt Events..................................................................................... 15-165
Setting Up the Receive Queue Filer Table .................................................... 15-165
Filer Example—802.1p Priority Filing.......................................................... 15-166
Filer Example—IP Diff-Serv Code Points Filing.......................................... 15-166
Filer Example—TCP and UDP Port Filing .................................................. 15-167
Priority-Based Queuing (PBQ)...................................................................... 15-168
Modified Weighted Round-Robin Queuing (MWRR) .................................. 15-169
Initialization................................................................................................... 15-172
Operation ....................................................................................................... 15-172
Contents
Title
Number
Page
xxxi
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