MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1323

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Index
Phase-locked loops (PLLs)
PIDn (process ID registers 0–2), see e500 core, registers
PIR (processor ID register), see e500 core, registers
PMCn (performance monitor counter registers 0–3), see e500
PMGC0 (performance monitor global control register 0), see
PMLCan (performance monitor local control registers
PMLCbn (performance monitor local control registers
Power management
Power-on reset (POR)
Freescale Semiconductor
events triggered by watchpoint monitor, 21-27
examples, 20-28
external signals, 20-3
features, 20-3
functional description, 20-11
interrupts, 20-11
interrupts (from PIC) to generate events, 10-31
masking interrupts (from PIC), 10-31
memory map/register definition, 20-3
overflow indication on TRIG_OUT, 21-25
overview, 20-2
threshold events, 20-12
POR status (global utilities), 19-4
block disable
DDR interface, 9-61
device low-power modes, 19-25–19-32
interrupts that cause wake-up, 10-3
overview, 1-20
PCI Express, 18-13–18-18, 18-68–18-69
PCI special-cycle operations, 17-64
see also Global utilities, power management
configuration
L2 cache/SRAM, 20-26
local bus controller (LBC), 20-26
memory target queue, 20-18
PCI/PCI-X common events, 20-21
burstiness event, 20-14
burstiness event counting, 20-28
simple event counting, 20-28
threshold event counting, 20-28
triggering event counting, 20-28
core, registers
e500 core, registers
a0–a3), see e500 core, registers
b0–b3), see e500 core, registers
block disable control (DEVDISR), 19-14, 19-27
LBC, 14-4
control and status register (POWMGTCSR), 19-16
READY negation, 4-2
boot ROM location, 4-13
boot sequencer configuration, 4-16
clock
e500 core PLL ratio, 4-12
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Processor version (PVR), 19-18
Programmable interrupt controller (PIC), see Interrupt
Protocols
PVR (processor version register), see e500 core, registers
Q
Quality of service (QoS), see eTSEC
R
Random number generator (RNG), see Security engine
RapidIO controller
READY signal, 4-2, 4-10, 21-24, 21-25
Registers
configuration reporting
debug modes summary, 21-3
hard reset, 4-8
output signal states during reset, 3-17
PCI Express, modes of operation, 18-4
reset configuration signals, 3-15
sequence of events, 4-9
PCI, see PCI/PCI-X controller, bus protocol
clocks
by acronym (memory-mapped registers)
configuration, control, and status, 2-10–2-14, 4-4
context ID, 21-23–21-24
DDR
CPU boot configuration, 4-15
DDR debug mode (ECC pins used for debug), 4-20, 21-3
eTSEC1 protocol, 4-18
eTSEC1–2 data width, 4-17
eTSEC3 protocol, 4-18
general-purpose (external system)
memory debug select (DDR or LBC), 4-20, 21-3
PCI data bus width, 4-19
PCI debug configuration, 21-3
PCI I/O impedance, 4-20
PCI/PCI-X arbiter configuration, 4-20
PCI/PCI-X, modes of operation, 17-67
PCI-X mode selection, 4-19
global utilities, 19-4, 19-6, 19-7, 19-8, 19-10, 19-11
and READY signal, 4-2, 4-10
controller (PIC), 1-15
(SEC)
minimum CCB frequency equation, 4-22
operation, 4-22
see Register Index
device-specific utilities, 2-13
general utilities, 2-12
programmable interrupt controller (PIC) space, 2-13
system/CCB PLL ratio, 4-11
configuration—LAD[0:31] (GPPORCR), 4-21
Index-15
Q–R