MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1261

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
0x140–
0x150–
0xBFC
0xE4C
0x14C
0xBF4
0xBF8
0xE00
0xE04
0xE08
0xE20
0xE24
0xE28
0xE40
0xE44
0xE48
0xE50
0xE54
0xE58
0x00C
0x147
0x148
0x000
0x004
0x008
0x010
0x014
Offset
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Reserved
DDR_INIT_ADDRESS—DDR training initialization address
DDR_INIT_EXT_ADDRESS—DDR training initialization
extended address
Reserved
DDR_IP_REV1—DDR IP block revision 1
DDR_IP_REV2—DDR IP block revision 2
DATA_ERR_INJECT_HI—Memory data path error injection
mask high
DATA_ERR_INJECT_LO—Memory data path error injection
mask low
ECC_ERR_INJECT—Memory data path error injection mask
ECC
CAPTURE_DATA_HI—Memory data path read capture high
CAPTURE_DATA_LO—Memory data path read capture low
CAPTURE_ECC—Memory data path read capture ECC
ERR_DETECT—Memory error detect
ERR_DISABLE—Memory error disable
ERR_INT_EN—Memory error interrupt enable
CAPTURE_ATTRIBUTES—Memory error attributes capture
CAPTURE_ADDRESS—Memory error address capture
CAPTURE_EXT_ADDRESS—Memory error extended
address capture
ERR_SBE—Single-Bit ECC memory error management
I2CADR—I
I2CFDR—I
I2CCR—I
I2CSR—I
I2CDR—I
I2CDFSRR—I
2
2
2
C status register
C control register
C data register
2
2
C frequency divider register
C address register
2
C digital filter sampling rate register
Table B-1. Memory Map (continued)
Register
Block Base Address: 0x0_3000
Block Base Address: 0x0_3000
I
I
2
2
C1 Registers
C2 Registers
I
2
C
Complete List of Configuration, Control, and Status Registers
Access
Mixed
Mixed
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
w1c
—
—
R
R
0x nnnn _ nnnn
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
0x0000_0000
Reset
0x00
0x00
0x00
0x81
0x00
0x10
—
—
1
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B-3