MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1169

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MPC8533EVTAQGA

Manufacturer Part Number
MPC8533EVTAQGA
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTAQGA

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.0GHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8533EVTAQGA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Freescale Semiconductor
10–12
17–19
20–21
22–24
25–26
27–31
Bits
13
14
15
16
PCI_ARB
PCI_SPD
IO_SEL
RTYPE
Name
ECP3
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
I/O port selection mode (See
000 All PCI Express ports powered down
001 Reserved
010 PCI Express port 1 active, PCI Express port 2 and 3 powered down
011 Reserved
100 PCI Express port 1 and 2 active, PCI Express port 3 powered down
101 Reserved
110 All PCI Express active
111 Reserved
PCI Express 1:
RX lane[0:3] -> SD1_RX[0:3]
TX lane [0:3] -> SD1_TX[0:3]
PCI Express 2:
RX lane[0:3] -> SD1_RX[4:7]
TX lane [0:3] -> SD1_TX[4:7]
PCI Express 3:
RX lane[0] -> SD2_RX[0]
TX lane [0] -> SD2_TX[0]
Reserved
PCI arbiter enable (See
0 PCI arbiter is disabled
1 PCI arbiter is enabled
Reserved
PCI speed (See
0 PCI set for low speed operation—PCI below 33MHz
1 PCI set for normal speed operation—PCI at or above 33MHz
Reserved
eTSEC3 controller protocol (See
00 The eTSEC3 controller operates using the 8-bit FIFO protocol.
01 The eTSEC3 controller operates using the MII protocol (or RMII if configured in reduced mode).
10 The eTSEC3 controller operates using the GMII protocol (or RGMII if configured in reduced mode).
11 The eTSEC3 controller operates using the TBI protocol (or RTBI if configured in reduced mode).
Reserved
DRAM Type (See
00 Low power DDR I
01 DDR I
10 Reserved
11 DDR II
Reserved
Table 19-7. PORDEVSR Field Descriptions (continued)
Section 4.4.3.15, “PCI Speed
Section 4.4.3.9, “DDR SDRAM
Section 4.4.3.17, “PCI Arbiter
Section 4.4.3.6, “I/O Port
Section 4.4.3.13, “eTSEC3
Description
Configuration.”)
Type.”)
Configuration.”)
Selection.”)
Protocol.”)
Global Utilities
19-9

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