MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 519

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
this register is merely a trigger causing the DEU to process the final block of a message, allowing it to
signal DONE.
Address DEU 0x3_2050
Access: Write-only
0
63
R
W
DEU EU-Go
Reset
All zeros
Figure 12-20. DEU EU Go Register
12.4.2.9
DEU IV Register (DEUIV)
For CBC mode, the initialization vector is written to and read from the DEU IV register. The value of this
register changes as a result of the encryption process and reflects the context of DEU. Reading this
memory location while the module is processing data generates an error interrupt.
12.4.2.10 DEU Key Registers 1–3 (DEUK n )
The DEU uses three write-only key registers to perform encryption and decryption. In single DES mode,
only key register 1 may be written. The value written to key register 1 is simultaneously written to key
register 3, auto-enabling the DEU for 112-bit triple DES if the key size register indicates 2 key 3DES is to
be performed (key size = 16 bytes). To operate in 168-bit triple DES, key register 1 must be written first,
followed by the write of key register 2, and then key register 3.
Reading any of these memory locations generates an address error interrupt.
12.4.2.11 DEU FIFOs
DEU uses an input FIFO/output FIFO pair to hold data before and after the encryption process. These
FIFOs are multiply addressable, but those multiple addresses point only to the appropriate end of the
appropriate FIFO. A write to anywhere in the DEU FIFO address space causes the 64-bit-word to be
pushed onto the DEU input FIFO, and a read from anywhere in the DEU FIFO Address space causes a
64-bit-word to be popped off of the DEU output FIFO. Overflows and underflows caused by reading or
writing the DEU FIFOs are reflected in the DEU interrupt status register.
12.4.3
ARC Four Execution Unit (AFEU)
This section contains details about the ARC four execution unit (AFEU), including modes of operation,
status and control registers, S-box memory, and FIFOs.
Most of the registers described here would not normally be accessed by the host. They are documented
here mainly for debug purposes. In typical operation, the AFEU is used through channel-controlled access,
which means that most reads and writes of AFEU registers are directed by the SEC channels. Driver
software performs host-controlled register accesses on only a few registers for initial configuration and
error handling.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Freescale Semiconductor
12-41