MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 754

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
Table 15-6
15.5.3.1.3
Interrupt events cause bits in the IEVENT register to be set. Software may poll this register at any time to
check for pending interrupts. If an event occurs and its corresponding enable bit is set in the interrupt mask
register (IMASK), the event also causes a hardware interrupt at the PIC. A bit in the interrupt event register
is cleared by writing a 1 to that bit position. A write of 0 has no effect.
Each eTSEC can issue three kinds of hardware interrupt to the PIC:
15-24
10–15
16–23
24–31
Bits
0–9
1. Transmit interrupts—Issued whenever bits TXB or TXF of IEVENT are set to 1 and either transmit
2. Receive interrupts—Issued whenever bits RXB or RXF of IEVENT are set to 1 and either receive
3. Error and diagnostic interrupts—Issued whenever bits MAG, GTSC, GRSC, TXC, RXC, BABR,
interrupt coalescing is disabled or the interrupt coalescing thresholds have been met for TXF. To
negate this hardware interrupt, software must clear both TXB and TXF bits.
interrupt coalescing is disabled or the interrupt coalescing thresholds have been met for RXF. To
negate this hardware interrupt, software must clear both RXB and RXF bits.
BABT, LC, CRL, FIR, FIQ, DPE, PERR, EBERR, TXE, XFUN or BSY of IEVENT are set to 1.
Software must clear all of these bits to negate an error/diagnostic hardware interrupt.
— Magic Packet reception event is: MAG
TSEC_CFG
TSEC_INT
describes the fields of the TSEC_ID2 register.
Name
—
—
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Interrupt Event Register (IEVENT)
Reserved
Interface mode support.
Reserved
Value identifies configuration options of the eTSEC.
00 eTSEC multiple ring, Rx TOE, Filer and Tx TOE supports are off
F0 eTSEC multiple ring, Rx TOE, Filer and Tx TOE supports are on
30 eTSEC multiple ring support is OFF and Rx TOE, Filer and Tx TOE supports are on
50 eTSEC multiple ring and filer supports are OFF and Rx TOE and Tx TOE supports are on
Table 15-6. TSEC_ID2 Field Descriptions
Bit
10
11
12
13
14
15
0 Ethernet mode not supported
1 Ethernet mode supported
0 FIFO mode not supported
1 FIFO mode supported
Reserved
0 Can be configured to run in FIFO 8-bit mode
1 FIFO 8-bit mode off
0 Can be configured to run in Ethernet normal/full mode
1 Ethernet normal/full mode off
0 Can be configured to run in Ethernet reduced mode
1 Ethernet reduced mode off
Description
Mode
Freescale Semiconductor