MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 928

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
Table 15-161
Table 15-162
15-198
Set up the MII Mgmt for a write cycle to external the PHY AN Advertisement register (write the PHY address and Register
eTSEC Signals
The AN Advertisement register is at offset address 0x04 from the external PHY address. (in this case 0x11)
TX_CLK
Write to MII Mgmt Control with 16-bit data intended for the external PHY AN Advertisement register,
MDIO
MDC
describes the shared signals for the RMII interface.
describes the register initializations required to configure the eTSEC in RMII mode.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Sum
set system clock divide by 14 for example to insure that MDC clock speed = 2.5 MHz
(Used to setup Reduced-Pin mode = 1, and TBIM = 0,statistics enable = 1)
Where u must be selected by the user for proper system configuration.
MACSTNADDR2[0110_0000_0000_0010_0000_0000_0000_0000]
MACSTNADDR1[0100_0011_0110_0101_1000_0111_1000_1100]
I/O
I/O
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
MIIMIND ---> [0000_0000_0000_0000_0000_0000_0000_0000]
O
I
Table 15-162. RMII Mode Register Initialization Steps
MACCFG1[1000_0000_0000_0000_0000_0000_0000_0000]
MACCFG1[0000_0000_0000_0000_0000_0000_0000_0000]
MACCFG2[0000_0000_0000_0000_0111_0010_0000_0101]
MIIMCON[0000_0000_0000_0000_u0uu_uuuu_uuuu_uuuu]
MIIMCFG[0000_0000_0000_0000_0000_0000_0000_1101]
MIIMADD[0000_0000_0000_0000_0001_0001_0000_0100]
ECNTRL[0000_0000_0000_0000_0001_0000_0001_0000]
Read MII Mgmt Indicator register and check for Busy = 0,
Read MII Mgmt Indicator register and check for Busy = 0,
Signals
Perform an MII Mgmt write cycle to the external PHY.
No. of
This indicates that the eTSEC MII Mgmt bus is idle.
This indicates that the write cycle was completed.
1
1
1
3
Check to see if MII Mgmt write is complete.
Table 15-161. Shared RMII Signals
Setup the MII Mgmt clock speed,
to 02608C:876543 for example
to 02608C:876543 for example
(I/F Mode = 2, Full Duplex = 1)
Initialize MAC Station Address
Initialize MAC Station Address
GMII Signals
REF_CLK
Initialize MACCFG2,
MDIO
MDC
Initialize ECNTRL,
Clear Soft_Reset,
Set Soft_Reset,
Sum
address),
I/O
I/O
O
I
Signals
No. of
1
1
1
3
Management interface clock
Management interface I/O
Reference clock
Function
Freescale Semiconductor