MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1157

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

generation of beacon; therefore, as an alternative, the device can use one of the GPIO signals as an enable
to an external tristate buffer to generate a WAKE signal, as shown in
In RC mode, the WAKE signal from the EP device can be connected to one of the external interrupt inputs
to service the WAKE request.
18.4.5
When a hot reset condition occurs, the controller (in both RC and EP mode) will initiate a clean-up of all
outstanding transactions and returns to an idle state. All configuration register bits that are non-sticky will
be reset. Link training will take place subsequently. The device is permitted to generate a hot reset
condition on the bus when it is configured as an RC device by setting the “Secondary Bus Reset” bit in the
Bridge Control Register in the configuration space. As an EP device, it is not permitted to generate a hot
reset condition; it can only detected a hot reset condition and initiates the clean-up procedure appropriately.
18.5
18.5.1
In normal boot mode (cfg_cpu_boot = 1), the core is allowed to boot and configure the device. During this
time, the PCI Express interface will retry all inbound PCI Express configuration transactions. When the
core has configured the device to a state where it can accept inbound PCI Express configuration
transactions, the boot code should set the CFG_READY bit in the PEX_CFG_READY register after
which inbound PCI Express configuration transactions will be accepted. Refer to
“Configuration Ready
In boot hold-off mode (cfg_cpu_boot = 0), the core is prevented from fetching its first instruction by
withholding its internal bus grant. During this time, the PCI Express interface accepts all inbound PCI
Express configuration transactions which allows an external host/RC to configure the device. When the
external host/RC has configured the device to a state where it can allow the core to fetch code from the
boot vector, it sets the MCMPCR[PORT0_EN] bit after which the core is granted the internal bus.
Freescale Semiconductor
Initialization/Application Information
Hot Reset
Boot Mode and Inbound Configuration Transactions
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
PCI Express controller
Register—0x4B0,” for more information about the CFG_READY bit.
in EP mode
Figure 18-130. WAKE Generation Example
GPOUT[24]
Figure
18-130.
WAKE
PCI Express Interface Controller
Section 18.3.10.18,
18-109