MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 258

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Core Register Summary
6.13.1.3
6-42
Reset
40–41
42–63
32–33 DAC1US Data address compare 1 user/supervisor mode
34–35 DAC1ER Data address compare 1 effective/real mode
36–37 DAC2US Data address compare 2 user/supervisor mode
SPR 310
Bits
Bits
W
R DAC1U
32
IAC12M Instruction address compare 1/2 mode
Name
Name
S
—
33
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Debug Control Register 2 (DBCR2)
DAC1E
34
00 Exact address compare. IAC1 debug events can occur only if the address of the instruction fetch is
01 Address bit match. IAC1 and IAC2 debug events can occur only if the address of the instruction fetch,
10 Inclusive address range compare. IAC1 and IAC2 debug events occur only if the address of the
11 Exclusive address range compare. IAC1 and IAC2 debug events occur only if the address of the
Reserved, should be cleared.
00 DAC1 debug events can occur
01 Reserved
10 DAC1 debug events can occur only if MSR[PR] = 0.
11 DAC1 debug events can occur only if MSR[PR] = 1.
00 DAC1 debug events are based on effective addresses.
01 Reserved on the e500
10 DAC1 debug events are based on effective addresses and can occur only if MSR[DS] = 0.
11 DAC1 debug events are based on effective addresses and can occur only if MSR[DS] = 1.
00 DAC2 debug events can occur.
01 Reserved
10 DAC2 debug events can occur only if MSR[PR] = 0.
11 DAC2 debug events can occur only if MSR[PR] = 1.
R
If IAC1US ≠ IAC2US or IAC1ER ≠ IAC2ER, results are boundedly undefined.
equal to the value specified in IAC1. IAC2 debug events can occur only if the address of the instruction
fetch is equal to the value specified in IAC2.
ANDed with the contents of IAC2 are equal to the contents of IAC1, plus ANDed with the contents of
IAC2.
If IAC1US ≠ IAC2US or IAC1ER ≠ IAC2ER, results are boundedly undefined.
instruction fetch is greater than or equal to the value specified in IAC1 and less than the value specified
in IAC2.
If IAC1US ≠ IAC2US or IAC1ER ≠ IAC2ER, results are boundedly undefined.
instruction fetch is less than the value specified in IAC1 or is greater than or equal to the value specified
in IAC2.
35
DAC2U
36
S
Table 6-36. DBCR1 Field Descriptions (continued)
37
Figure 6-52. Debug Control Register 2 (DBCR2)
DAC2E
38
Table 6-37. DBCR2 Field Descriptions
R
39
DAC12
40
M
41 42
All zeros
Description
Description
—
Access: Supervisor read/write
Freescale Semiconductor
63