MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 548

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Security Engine (SEC) 2.1
must be a multiple of 256 bits (32 bytes). If an improper data size is written, a data size error is generated.
Only the lowest 3, 7, or 8 bits of the data size register are checked to determine if there is a data size error.
Since all upper bits are ignored, the entire message length (in bits) can be written to this register.
This register is cleared when the AESU is reset or re-initialized.
Writing to this register signals the AESU to start processing data from the input FIFO as soon as it is
available. If the value of data size is modified during processing, a context error is generated.
12.4.6.4
This register allows three levels of reset for the AESU, as defined by the three self-clearing bits:
Table 12-40
12-70
0–60
Bits Name
Address AESU 0x3_4010
Address AESU 0x3_4018
61
62
63
Reset
Reset
W
W
R
R
SR
MI
—
RI
0
0
Reserved
Reset interrupt. Writing this bit active high causes AESU interrupts signaling DONE and ERROR to be reset. It
further resets the state of the AESU interrupt status register.
0 Don’t reset
1 Reset interrupt logic
Module initialization is nearly the same as software reset, except that the interrupt control register remains
unchanged. This module initialization includes execution of an initialization routine, completion of which is
indicated by the RESET_DONE bit in the AESU status register
0 Don’t reset
1 Reset most of AESU
Software reset is functionally equivalent to hardware reset (the RESET signal), but only for AESU. All registers
and internal state are returned to their defined reset state. Upon negation of SW_RESET, the AESU enters a
routine to perform proper initialization of the parameter memories. The RESET_DONE bit in the AESU status
register indicates when this initialization routine is complete
0 Don’t reset
1 Full AESU reset
describes AESU reset control register fields.
AESU Reset Control Register (AESURCR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 12-40. AESU Reset Control Register Field Descriptions
Figure 12-50. AESU Reset Control Register
Figure 12-49. AESU Data Size Register
—
—
All zeros
All zeros
Description
47 48
60
Freescale Semiconductor
61
RI
Data Size
Access: Read/write
Access: Read/write
MI
62
SR
63
63