MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 714

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Local Bus Controller
Figure 14-78
14.5.5
In many applications, SDRAM provides sufficient performance for the local bus. However, especially in
networking applications, memory access patterns are often random and SDRAM is not optimized for that
case. ZBT SRAMs have been designed to optimize the performance in networking applications. This
section describes how to interface to ZBT SRAMs.
to generate control signals. The same interfacing is used for pipelined and flow-through versions of ZBT
SRAMs. However different UPM patterns must be generated for those cases. Because ZBT SRAMs will
mostly be used by performance-critical applications, we assume here that, typically, the maximum width
of the local bus of 32 bits will be used.
ZBT SRAMs allow different configurations. For the local bus the burst order should be set to linear burst
order by tying the mode signal to GND; CKE should also be tied to ground.
14-96
Local Bus Interface
LSDDQM[0:3]
Interfacing to ZBT SRAM
shows a connection diagram.
LAD[0:31]
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
LSDRAS
LSDCAS
LDP[0:3]
LSDA10
LSDWE
LPBSE
LCKE
LCLK
LCS n
LALE
Latch
Figure 14-78. Parity Support for SDRAM
DQM0
CAS
CS
RAS
WE
BA[1:0]
DQM
CKE
CLK
ADDR[12:0]
A10
32M × 8
SDRAM
DATA[0:7]
• • •
DQ[0:7]
Figure 14-79
• • •
×4
DQM3
shows the connections. The UPM is used
CAS
CS
RAS
WE
BA[1:0]
DQM
CKE
CLK
ADDR[12:0]
A10
DATA[24:31]
SDRAM
32M × 8
DQ[0:7]
Freescale Semiconductor
CAS
CS
RAS
WE
BA[1:0]
DQM
CKE
CLK
ADDR[12:0]
A10
DP[0:3]
SDRAM
32M × 4
DQ[0:3]