MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 697

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

14.5
14.5.1
14.5.1.1
To save signals on the local bus, address and data are multiplexed onto the same 32 bit bus. An external
latch is needed to demultiplex and reconstruct the original address. No external intelligence is needed,
because the LALE signal provides the correct timing to control a standard logic latch. The LAD signals
can be directly connected to the data signals of the memory/peripheral.
Transactions on the local bus start with an address phase, where the LBC drives the transaction address on
the LAD signals and asserts the LALE signal. This can be used to latch the address and then the LBC can
continue with the data phase.
The LBC supports port sizes of 8,16, and 32 bits. For devices smaller than 32 bits, transactions must be
broken down. For this reason, LA[30:31] are driven non-multiplexed. For 8-bit devices, LA[30:31] should
be used and for 16-bit devices, LA[30] should be used. 32-bit devices use neither of these signals.
In addition, the LBC supports burst transfers (not in the GPCM machine). LA[27:29] are the burst
addresses within a natural 32-byte burst. To minimize the amount of address phases needed on the local
bus and to optimize the throughput, those signals are driven separately and should be used whenever a
device requires the five least significant addresses. Those should not be used from LAD[27:31].
All other addresses, A[0:26], must be reconstructed through the latch.
Freescale Semiconductor
Initialization/Application Information
Interfacing to Peripherals
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Multiplexed Address/Data Bus and Non-Multiplexed Address Signals
Local Bus Interface
LAD[0:31]
LA[27:31]
LALE
Figure 14-68. Multiplexed Address/Data Bus
Muxed Address/Data
Non-Muxed Address
D
LE
Latch
Q
D[0:31]
A[0:26]
A[27:31]
Local Bus Controller
14-79