MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1317

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Index
Interrupts
IRQ[0:11] (interrupt request 0–11) signals, 10-8
Freescale Semiconductor
reset of PIC, 10-19, 10-52
reset processor from software, 10-20
signals summary, 10-7
simultaneous interrupts, priorities, 10-49
sources of interrupts, 10-5
spurious vector generation, 10-22, 10-50
vendor identification, 10-20
DDR, 9-37
DMA, 16-10–16-13, 16-15, 16-20, 16-24, 16-33
DUART
e500 core
ECM interrupt register (ECM error enable
eTSEC, 15-152–15-155
I
IRQ[9:11] signal select, 19-13, 19-33
LBC interrupt register, 14-26
PCI/PCI-X error enable register, 17-26
performance monitor (PIC), 20-20
power management and interrupts (global utilities), 19-31
security engine (SEC), 12-103–12-104, 12-108
see also Interrupt controller (PIC)
2
C interface
message registers, 10-33–10-35
non-accessible registers
per-CPU registers, 10-43–10-47
performance monitor mask registers, 10-31–10-33
summary registers, 10-27–10-31
see also Signals, PIC
internal (to PIC) interrupt destinations, 10-28, 10-29,
internal (to PIC) interrupt sources, 10-6
interrupt control logic, 13-23
interrupt enable and control registers, 13-9–13-11
registers, 6-17–6-22
interrupt registers, 15-24–15-29
calling address match condition, 11-6
flowchart for interrupt service routine, 11-24
interrupt after transfer, 11-22
interrupt enable bit (I2CCR[MIEN]), 11-8
interrupt on START, 11-22
interrupt pending status bit (I2CSR[MIF]), 11-10
interrupt-driven byte-to-byte transfers, 11-2
read of last byte, 11-23
slave mode interrupt service routine guidelines, 11-23
registers, 12-110–12-112
in-service register (ISR), 10-49
interrupt pending register (IPR), 10-47
interrupt request register (IRR), 10-47
register—EEER), 8-7
for slave transmitter routine, 11-24
loss of arbitration, 11-24
10-30, 10-31
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
IRQ[9:11] signal select
IRQ_OUT (interrupt request out) signal, 10-8, 10-27
IVORn (interrupt vector offset registers), see e500 core,
IVPR (interrupt vector prefix register), see e500 core,
J
JEDEC SDRAM commands (LBC), 14-49
JTAG test access port
L
L1CFG0–1 (L1 cache configuration registers 0–1), see e500
L1CSR0–1 (L1 cache status and control registers 0–1), see
L2 cache/SRAM
LA[27:31] (LBC non-multiplexed address) signals, 14-7
LAD[0:31] (LBC multiplexed address/data) signals, 14-7
global utilities, 19-13
signals summary, 21-5
allocation of lines, 7-32
block diagram, 7-1
coherency rules, 7-28
error handling registers, 7-17
error injection, 7-18
external writes, see stashing
flash clearing, instruction and data locks, 7-31
locking
memory map/register definition, 7-8
memory-mapped SRAM
memory-mapped windows, 2-4
operation, 7-33
overview, 7-1
performance monitor events, 20-26
PLRU bit update considerations, 7-32
register descriptions, 7-10–7-25
replacement policy, 7-31
SRAM features, 7-2
stashing, 7-25
state transitions, 7-35
timing, 7-27
registers
registers
see also Signals, JTAG, 21-5
core, registers
e500 core, registers
clearing locks on selected lines, 7-30
entire, 7-29
programmed memory ranges, 7-30
selected lines, 7-30
with stale data, 7-31
coherency rules, 7-29
due to core-initiated transactions, 7-35
due to system-initiated transactions, 7-38
Index-9
J–L