MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 401

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

10.1.4.2
The PIC unit provides a mechanism to support alternate external interrupt controllers such as the PC/AT
compatible 8259 interrupt controller architecture. After a hard reset, the PIC unit defaults to pass-through
mode, in which active-high interrupts from external source IRQ0 are passed directly to the e500 core, as
shown in
external interrupt controller can be connected to IRQ0 and cause direct interrupts to the processor. The PIC
does not perform a vector fetch from an 8259 interrupt controller.
When pass-through mode is enabled, the internally-generated interrupts shown in
forwarded to the e500 core. Instead, the PIC passes the raw interrupts from the internal sources to
IRQ_OUT.
Note that when the PCI Express controller is configured as an endpoint (EP) device, the irq_out signal
from the PIC may used to automatically generate an outbound PCI Express MSI transaction toward the
remote interrupt controller resource on the root complex (RC). See
Generation.”
Note that in pass-through mode, interrupts generated by the PIC itself (global timers, interprocessor, and
message register interrupts) cannot be used. If internal or PIC-generated interrupts must be reported
internally to the processor, pass-through mode must be disabled.
10.1.5
Aside from the sources of machine check, unconditional debug event, and reset interrupts to the core
described in
Freescale Semiconductor
•
•
•
•
PC/AT-Compatible
PC/AT-Compatible
8259 Interrupt
8259 Interrupt
External—Off-chip signals, IRQ[0:11]
Internal—On-chip. Sources are L2, ECM, DDR, LBC, DMA, PCI Express, eTSEC1–2, DUART,
performance monitor, security engine, and I
Global timers—From inside the PIC
Inter-processor (IPI)—Intended for communication between different processor cores on the same
device. Used only for self-interrupt in single-core devices.
Controller
Controller
Table
External
External
Table
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Interrupt Sources
Pass-Through Mode (GCR[M] = 0)
10-2; all other external interrupt signals are ignored. Thus, the interrupt signal from an
10-1, the PIC unit can receive interrupts from six different sources as follows:
(Disabled)
(Disabled)
IRQ[1:11]
IRQ[1:11]
IRQ_OUT
IRQ0
IRQ0
Figure 10-2. Pass-Through Mode Example
Express
PCI
2
irq_out
C.
GCR[M] = 0
PIC
Section 18.4.2.1.2, “Hardware MSI
int
int
Internal interrupts (see
Table
PIC-generated interrupts)
e500 Core
e500 Core
10-3) (not including
Programmable Interrupt Controller
Table
10-5, are not
10-5