MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 840

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Enhanced Three-Speed Ethernet Controllers
15.5.3.9
This section describes the two eTSEC DMA attribute registers.
15.5.3.9.1
The attribute register defines memory access attributes and transaction types used to access buffer
descriptors, to write receive data, and to read transmit data. Snoop enable attributes may be set for reading
buffer descriptors and for reading transmit data. Buffer descriptors may be written with attributes that
cause allocation into the L2 cache. Similarly, broad sections of a receive frame header may have attributes
attached that cause allocation in the L2 cache. This process of specifying a region of each frame to stash
into the L2 cache is referred to as extraction, which is specified in conjunction with register ATTRELI.
ATTR[ELCWT] only has meaning if ATTRELI[EL] is non-zero. It is important to note that even though
portions of received frames may be stashed to L2 cache, this is only a performance optimization as entire
frames are still written to off-chip memory regardless of settings in ATTR.
15-110
30–31
Bits
23
24
25
26
27
28
29
CRCAPP Append a CRC (CRC-32 algorithm, as per IEEE Std. 802.3) to the end of every transmitted frame.
CRCCHK Check the CRC (CRC-32 algorithm, as per IEEE Std. 802.3) at the end of every frame.
Name
SIGM
RFC
LPB
TFC
FFC
—
DMA Attribute Registers
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Attribute Register (ATTR)
Loopback enable.
0 Do not loopback data in the FIFO interface.
1 Loopback transmitted data to the FIFO receiver rather than outputting transmitted data to signals.
Enable receive flow control. Setting FFC overrides this bit.
0 Do not allow the FIFO receiver to assert link-level flow control if eTSEC requires it.
1 Allow the FIFO receiver to assert link-level flow control if eTSEC requires it. This is the default setting.
Enable transmit flow control.
0 Do not allow the FIFO transmitter to assert link-level flow control if transmit data is unavailable, resulting
1 Allow the FIFO transmitter to assert link-level flow control if transmit data is unavailable and SIGM = 01.
Force flow control. This can be used by software to stop reception on the FIFO interface.
0 Do not assert link-level flow control via the RXFC signal unless eTSEC requires flow control.
1 Force flow control on the RXFC signal in encoded FIFO packet mode regardless of eTSEC pause
0 Do not automatically append a CRC to transmitted frames. Allow TxBD[TC], if set, to control when a
1 Automatically append a CRC to transmitted frames. Ignore TxBD[TC].
0 Do not automatically check the last 4 bytes of received frames for a valid CRC.
1 Automatically check the last 4 bytes of received frames for a valid CRC. If a CRC error is detected, or
Reserved
FIFO signaling mode. Determines how the GMII signals are interpreted as framing signals.
00 GMII style mode.
01 Encoded packet mode.
10 Reserved
11 Reserved
in underruns.
This is the default setting.
requirements.
CRC is appended.
insufficient data is received to recover the CRC, the RxBD[CR] bit will be set.
Table 15-105. FIFOCFG Field Descriptions (continued)
Description
Freescale Semiconductor