MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1029
MPC8533EVTAQGA
Manufacturer Part Number
MPC8533EVTAQGA
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTAQGA
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.0GHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC8533EVTAQGA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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Figure 17-49
Figure 17-50
17.4.2.7.2
This section describes PCI single-beat write transactions, and PCI burst write transactions. A PCI write
transaction starts with the address phase, occurring when an initiator asserts PCI_FRAME. A write
transaction is similar to a read transaction except no turnaround cycle is needed following the address
phase because the initiator provides both address and data. The data phases are the same for both read and
write transactions. Although not shown in the figures, the initiator must drive the PCI_C/BE[3:0] signals,
even if the initiator is not ready to provide valid data (PCI_IRDY negated).
Freescale Semiconductor
PCI_DEVSEL
PCI_DEVSEL
PCI_FRAME
PCI_FRAME
PCI_TRDY
PCI_TRDY
PCI_C/BE
PCI_IRDY
PCI_C/BE
PCI_IRDY
illustrates a PCI single-beat read transaction.
illustrates a PCI burst read transaction.
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
SYSCLK
SYSCLK
PCI_AD
PCI_AD
PCI Write Transactions
Figure 17-49. PCI Single-Beat Read Transaction
ADDR
ADDR
CMD
CMD
Figure 17-50. PCI Burst Read Transaction
Byte Enables 1
DATA1
Byte Enables
Byte Enables 2
DATA2
DATA
PCI Bus Interface
17-51
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