MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 1168

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MPC8533EVTAQGA

Manufacturer Part Number
MPC8533EVTAQGA
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTAQGA

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.0GHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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Quantity
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Part Number:
MPC8533EVTAQGA
Manufacturer:
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Quantity:
10 000
Global Utilities
19.4.1.4
Shown in
Section 4.4.3.10, “eTSEC1 Width,” Section 4.4.3.11, “eTSEC3 Width,” and Section 4.4.3.17, “PCI
Arbiter Configuration.”
Table 19-7
19-8
Offset 0xE_000C
Reset
Reset
Bits
6–7
8–9
0
1
2
3
4
5
W
W
R
R PCI_SPD
ECW1
ECW1
ECW2
Figure
Name
ECP1
16
n
0
0
describes the bit settings of PORDEVSR.
POR Device Status Register (PORDEVSR)
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
19-4, PORDEVSR reports other POR settings for I/O devices as described in
ECW2
eTSEC1 controller width (See
0 Reduced interfaces for eTSEC1(RGMII, RTBI, or 8-bit FIFO on eTSEC1)
1 Full interfaces for eTSEC1(MII, GMII, TBI, or 16-bit FIFO on eTSEC1)
eTSEC3 controller width (See
0 Reduced interfaces for eTSEC3 (RGMII, RTBI)
1 Full interface for eTSEC3 (MII, GMII, TBI)
note: FIFO mode on eTSEC3 is always 8-bits regardless of ECW2.
Reserved
Reserved
Reserved
Reserved
eTSEC1 controller protocol (See
00 The eTSEC1 controller operates using the 16-bit FIFO protocol (or 8-bit FIFO if configured in reduced
01 The eTSEC1 controller operates using the MII protocol (or RMII if configured in reduced mode).
10 The eTSEC1 controller operates using the GMII protocol (or RGMII if configured in reduced mode).
11 The eTSEC1 controller operates using the TBI protocol (or RTBI if configured in reduced mode).
Reserved
17
1
n
0
mode).
Figure 19-4. POR Device Status Register (PORDEVSR)
0
0
2
Table 19-7. PORDEVSR Field Descriptions
19
0
0
20
0
n
ECP3
Section 4.4.3.10, “eTSEC1
Section 4.4.3.11, “eTSEC3
21
Section 4.4.3.12, “eTSEC1
0
n
5
22
n
0
6
ECP1
7
n
0
Description
24
0
0
8
RTYPE
25
0
n
9
Width.”)
Width.”)
10
26
n
n
Protocol.”)
27
n
0
IO_SEL
12
n
0
Freescale Semiconductor
13
Access: Read Only
0
0
PCI_ARB
14
n
0
15
31
0
0

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