MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 637

• Manufacturer Part Number: MPC8533EVTAQGA
• Description: MPU POWERQUICC 783-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8533EVTAQGA

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 1.0GHz
• Voltage: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Package / Case: 783-BBGA, FCBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

Freescale Semiconductor
10–12
14–17
18–21
22–25
26–31
Bits
13
Name
G0CL General line 0 control. Determines which logical address line can be output to the LGPL0 signal when the
GPL4 LGPL4 output line disable. Determines how the LGPL4/LUPWAIT signal is controlled by the corresponding
MAD
WLF
RLF
TLF
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
UPM n is selected to control the memory access.
000 A12
001 A11
010 A10
011 A9
100 A8
101 A7
110 A6
111 A5
bits in the UPM n array. See
Read loop field. Determines the number of times a loop defined in the UPM n will be executed for a burst- or
single-beat read pattern or when M x MR[OP] = 11 (
0000 16
0001 1
0010 2
0011 3
...
1110 14
1111 15
Write loop field. Determines the number of times a loop defined in the UPM n will be executed for a burst- or
single-beat write pattern.
0000 16
0001 1
0010 2
0011 3
...
1110 14
1111 15
Refresh loop field. Determines the number of times a loop defined in the UPM n will be executed for a refresh
service pattern.
0000 16
0001 1
0010 2
0011 3
...
1110 14
1111 15
Machine address. RAM address pointer for the command executed. This field is incremented by 1 each time
the UPM is accessed, and the OP field is set to WRITE or READ. Address range is 64 words per UPM n .
Table 14-10. M x MR Field Descriptions (continued)
Value
0
1
Table
LGPL4/LUPWAIT
Signal Function
LUPWAIT (input)
LGPL4 (output)
14-28.
Description
RUN
Interpretation of UPM Word Bits
command)
G4T1/DLT3
G4T1
DLT3
G4T3/WAEN
WAEN
G4T3
Local Bus Controller
14-19