MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 22

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MPC8533EVTAQGA

Manufacturer Part Number
MPC8533EVTAQGA
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTAQGA

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.0GHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MPC8533EVTAQGA
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Paragraph
Number
12.6.1.1
12.6.1.2
12.6.2
12.6.2.1
12.6.2.2
12.6.2.3
12.6.2.4
12.6.3
12.6.4
12.6.5
12.6.5.1
12.6.5.2
12.6.5.3
12.6.5.4
12.6.5.5
12.6.5.6
12.6.5.7
12.7
13.1
13.1.1
13.1.2
13.2
13.2.1
13.2.2
13.3
13.3.1
13.3.1.1
13.3.1.2
13.3.1.3
13.3.1.4
13.3.1.5
13.3.1.6
13.3.1.7
13.3.1.8
13.3.1.9
13.3.1.10
xxii
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Power-Saving Mode................................................................................................... 12-115
Overview........................................................................................................................ 13-1
External Signal Descriptions ......................................................................................... 13-3
Memory Map/Register Definition ................................................................................. 13-4
Bus Transfers ......................................................................................................... 12-105
Snooping by Caches............................................................................................... 12-108
Controller Interrupts .............................................................................................. 12-108
Controller Registers ............................................................................................... 12-109
Features...................................................................................................................... 13-1
Modes of Operation ................................................................................................... 13-2
Signal Overview ........................................................................................................ 13-3
Detailed Signal Descriptions ..................................................................................... 13-3
Register Descriptions................................................................................................. 13-6
Channel Priority Arbitration .............................................................................. 12-105
Channel Round-Robin Arbitration .................................................................... 12-105
Arbitration for Use of the Controller and Buses................................................ 12-106
System Bus Master Reads ................................................................................. 12-107
System Bus Master Writes................................................................................. 12-107
System Bus Slave Transactions (Reads and Writes) ......................................... 12-107
EU Assignment Status Register (EUASR) ........................................................ 12-109
Interrupt Mask Register (IMR).......................................................................... 12-110
Interrupt Status Register (ISR) ...........................................................................12-111
Interrupt Clear Register (ICR) ........................................................................... 12-112
ID Register......................................................................................................... 12-113
IP Block Revision Register................................................................................ 12-113
Master Control Register (MCR) ........................................................................ 12-114
Receiver Buffer Registers (URBR0, URBR1) (ULCR[DLAB] = 0) .................... 13-6
Transmitter Holding Registers (UTHR0, UTHR1) (ULCR[DLAB] = 0) ............. 13-6
Divisor Most and Least Significant Byte Registers (UDMB and UDLB)
Interrupt Enable Register (UIER) (ULCR[DLAB] = 0)........................................ 13-9
Interrupt ID Registers (UIIR0, UIIR1) (ULCR[DLAB] = 0) ................................ 13-9
FIFO Control Registers (UFCR0, UFCR1) (ULCR[DLAB] = 0)....................... 13-11
Line Control Registers (ULCR0, ULCR1).......................................................... 13-12
Modem Control Registers (UMCR0, UMCR1)................................................... 13-14
Line Status Registers (ULSR0, ULSR1) ............................................................. 13-15
Modem Status Registers (UMSR0, UMSR1) ...................................................... 13-16
(ULCR[DLAB] = 1) .......................................................................................... 13-7
Contents
Chapter 13
DUART
Title
Freescale Semiconductor
Number
Page

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