MPC8533EVTAQGA Freescale Semiconductor, MPC8533EVTAQGA Datasheet - Page 645
MPC8533EVTAQGA
Manufacturer Part Number
MPC8533EVTAQGA
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8533VTALF.pdf
(112 pages)
2.MPC8533VTALF.pdf
(2 pages)
3.MPC8533VTALF.pdf
(16 pages)
4.MPC8533VTALF.pdf
(1332 pages)
Specifications of MPC8533EVTAQGA
Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
1.0GHz
Voltage
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Package / Case
783-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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Manufacturer
Quantity
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Part Number:
MPC8533EVTAQGA
Manufacturer:
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Quantity:
10 000
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Table 14-18
14.3.1.13
Figure 14-16
LBC error registers to update following any subsequent errors.
Freescale Semiconductor
10–11
13–31
Bits
3–4
6–7
12
0
1
2
5
8
9
Offset 0x0BC
Reset
WARA Write-after-read atomic (WARA) error interrupt enable
RAWA Read-after-write atomic (RAWA) error interrupt enable
Name
PARI
BMI
WPI
CSI
W
—
—
—
—
—
R
describes LTEIR fields.
0
shows the LTEATR. After LTEATR[V] has been set, software must clear this bit to allow
MPC8533E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Bus monitor error interrupt enable
0 Bus monitor error reporting is disabled.
1 Bus monitor error reporting is enabled.
Reserved
Parity error interrupt enable. Note that uncorrectable read errors may cause the assertion of core_fault_in ,
which causes the core to generate a machine check interrupt, unless it is disabled (by clearing HID1[RFXE]).
If RFXE is zero and this error occurs, LTEDR[PARD] must be cleared and PARI must be set to ensure that an
interrupt is generated. For more information, see
Register 1 (HID1).”
0 Parity error reporting is disabled.
1 Parity error reporting is enabled.
Reserved
Write protect error interrupt enable
0 Write protect error reporting is disabled.
1 Write protect error reporting is enabled.
Reserved
0 WARA error reporting is disabled.
1 WARA error reporting is enabled.
0 RAWA error reporting is disabled.
1 RAWA error reporting is enabled.
Reserved
Chip select error interrupt enable
0 Chip select error reporting is disabled.
1 Chip select error reporting is enabled.
Reserved
—
Transfer Error Attributes Register (LTEATR)
2
RWB
3
Figure 14-16. Transfer Error Attributes Register (LTEATR)
4
Table 14-18. LTEIR Field Descriptions
—
10 11
SRCID
All zeros
Description
15 16
Section 6.10.2, “Hardware Implementation-Dependent
PB
19 20
BNK
Access: Read/Write
27 28 29 30 31
Local Bus Controller
XA — V
14-27
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